What does IC design verification mean?
| IC design verification refers to the process of determining whether or not the design of a product, of a given development phase, satisfies the conditions imposed from the start. |
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| 2011-11-10 | FPGA design software touts quick debug, verification FPGA design software touts quick debug, verification |
| 2011-11-03 | Perform assertion-based verification in mixed-signal design Perform assertion-based verification in mixed-signal design |
| 2011-10-05 | Debug platform eases SoC design, verification Debug platform eases SoC design, verification |
| 2011-08-31 | Calypto acquires Catapult C for better integrated ESL flow Aiming to get all as many pieces of an integrated ESL design flow together, Calypto said it has acquired, in a yet undisclosed terms, Catapult C Synthesis from Mentor. |
| 2011-07-28 | IC design platform promises increased productivity IC design platform promises increased productivity |
| 2011-06-23 | Accellera, OSCI team up unifies EDA standards Accellera and OSCI are joining forces to create a single organization, a move that will accelerate development of system-level standards as well as chip design and verification standards. |
| 2011-06-03 | Synopsys, Rhode & Schwarz collaborate on LTE design Synopsys, Rhode & Schwarz collaborate on LTE design |
| 2011-05-23 | EDA supplier claims industry's first hierarchical 3D extractor Complementing top EDA vendors' design flows, H3D is an accurate 3D extractor that runs with sub-linear performance and delivers a hierarchical output that enables post-layout simulation speed up. |
| 2011-05-13 | Look at all angles when right-sourcing electronic designs Companies must right-source any design project, use its designers' experience, skills and bandwidth, or in cases where these are unavailable, look for best-in-class implementation and verification sources. |
| 2011-05-05 | NextOp, Nvidia ink license deal for BugScope NextOp Software and Nvidia have signed a multilicense agreement for the expanded use of the BugScope assertion synthesis product. |
| 2011-05-04 | Design software supports UVM Design software supports UVM |
| 2011-03-21 | ChipEstimate.com opens VIP microsite The microsite offered by Cadence Design Systems' ChipEstimate.com makes it easier for engineers to find the most up-to-date information and appropriate verification IP for their SoC and chip designs. |
| 2011-03-15 | Mentor enables signoff-quality verification during design Mentor enables signoff-quality verification during design |
| 2011-03-08 | SpringSoft software offers reusable behavior analysis database SpringSoft's Siloti Visibility Automation System claims a streamlined, easy-to-use flow for SoC verification and debug that speeds up design preparation time by at least 10X over previous releases. |
| 2011-02-25 | Broadcom picks Cadence platform for system verification Broadcom picks Cadence platform for system verification |
| 2011-02-07 | Verification design flow connects third-party PCB tools Verification design flow connects third-party PCB tools |
| 2011-02-01 | Accellera releases new EDA modeling standard The standards organization announced the approval of a new version of the Co-Emulation Modeling Interface (SCE-MI) specification as a new verification standard. |
| 2011-01-17 | Fujitsu auto electronics adopts Springsoft system SpringSoft's Certitude System is to be used by Fujitsu's automotive business unit to raise the quality of verification environments and I) design components required to develop automotive MCU solutions. |
| 2010-12-20 | Synopsys receives Taiwan innovation award Synopsys cited for contributions to growth of Taiwan's semiconductor business |
| 2010-11-03 | Ricoh licenses DeFacTo's DFT solution Ricoh Company Ltd announced the licensing of the HiDFT-Signoff Design-for-Test solution of DeFacTo Technologies SA. |
| 2010-10-29 | Fairchild adopts Magwel PTM tool Fairchild Semiconductor said it has chosen Magwel's Power Transistor Modeling tool for design and verification of its high current power devices. |
| 2010-10-18 | 3D modelling tool eases verification 3D modelling tool eases verification |
| 2010-09-23 | FPGA design tool debugs TMR, ensures safety FPGA design tool debugs TMR, ensures safety |
| 2010-09-20 | SMIC taps Cadence for design solutions SMIC taps Cadence for design solutions |
| 2010-08-27 | Magma Design Automation joins Si2's DFMC Magma Design Automation joins Si2's DFMC |
| 2010-08-26 | Physical verification tool licensing program eases 65nm transition Physical verification tool licensing program eases 65nm transition |
| 2010-07-26 | How to implement cost-effective headset design, verification How to implement cost-effective headset design, verification |
| 2010-07-08 | Opinion: Tsunami to hit electronics shore There's a tsunami to the vast electronics ocean. EDA might well be able to catch the wave—with a little bit of savvy, ingenuity and engineering know-how. |
| 2010-06-16 | Early verification and validation using model-based design Early verification and validation using model-based design |
| 2010-06-24 | Tips on reducing debug efforts Debug will get your attention one way or another. If you give it attention early in the development cycle, it will reduce the amount of time spent on debug later and in future designs. |
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