total search21 articles
|2008-05-15||LDO controllers drive NMOS, NPN pass transistors
Leadis Technology has released samples of a new family of LDO controllers designed to drive NMOS or NPN pass transistors.
|1998-11-01||Zero-delay logic addresses PC design challenges
Modular PC designs require the use of additional logic that adds to signal delay and power consumption. One can avoid this problem and satisfy isolation, translation, and multiplexing requirements using zero-delay bus switches.
|2005-12-01||New mem compilers keep Moore's Law alive
Memory compilers provide accurate estimation of area, performance, timing and power consumption for thousands of memory configurations.
|2005-06-01||Leakage power at 90nm and below
Learn more about the challenges and tools needed in addressing leakage power at 90nm and below in today's advanced designs
|2007-12-13||IMEC reports progress on high-k metal gates at 32nm
IMEC reported progress in improving the performance of planar CMOS using hafnium-based high-k dielectrics and tantalum-carbide metal gates targeting the 32nm CMOS node.
|2013-06-14||Imec presents RRAM, FinFET innovations
At this week's VLSI 2013 Technology Symposium, Imec presented improved quantitative statistical prediction of the RRAM operation as well as the the first strained germanium devices based on a Si-replacement process.
|2003-09-01||Identifying front-end challenges for 90nm design
FEOL scaling is about density improvement while simultaneously improving transistor performance
|2005-03-16||Guru plumbs nanotech in all dimensions
For the most part, nano research activities are not that futuristic, says Yoshio Nishi of Stanford University.
|2005-11-16||GbE transceivers ignite port-count explosion
Ethernet's increasing bandwidth requirement is driving switch-router equipment designers to build scalable systems.
|2006-01-16||Freescale upends thinking on transistor channels
A research scientist proposes a transistor with a silicon channel structure resembling a T turned on its head.
|2008-06-30||FAN5109 VCC bypass considerations to reduce voltage spikes
Smaller semiconductor geometries result in faster switching times, and higher frequency operation. However, faster switching times also result in larger voltage spikes. The focus of this document is to understand and mitigate VCC spikes when using the new FAN5109 driver.
|2000-09-27||Extending your backplane performance with GTLP
As wireless and wireline designs migrate toward higher and higher transmission rates, a system designer's challenges become increasingly difficult. This paper describes the GTLP as an enabling technology for designers who want to extend the performance of their backplanes.
|2002-08-16||ESD process shrinks I/Os along core path
This technical article discusses how ESD design technology can reduce I/Os along the IC core path.
|2002-11-28||Chipmakers bang away at metal gates
Technologists are girding for yet another major change in CMOS gate stack integration: the replacement of polysilicon gate electrodes with two metals for PMOS and NMOS transistors.
|2005-01-03||Analog switches beat bus switches in ultraportable devices
When designing ultraportable devices, analog switches are more efficient than any other ordinary bus switches.
|2007-07-16||AMCC fields dual-core PowerPC for high-end apps
The 90nm Titan is a dual-core PowerPC processor aimed at high-end embedded markets with a multiclocking NMOS transistor architecture that enables the device to do more work in an eight- to nine-stage pipeline.
|2007-01-30||Sematech unveils solution for high-k CMOS devices
In its quest for developing dual metal gates for high-k CMOS devices, chip-making R&D consortium Sematech has demonstrated high-k/metal gate stacks to build high-performance nMOS and pMOS transistors in CMOS configuration.
|2009-09-07||MOSFET driver suits automotive apps
The AUIRS2016S high-voltage power MOSFET high-side driver features an internal Vs-to-GND recharge NMOS.
|2000-12-12||A CMOS keyboard data entry system for bus oriented memory systems
This application note describes a keypad to binary data entry system for use with NMOS or CMOS memories, either in a minicomputer/microprocessor application or as a part of any logic system containing RAM.
|2008-01-25||45nm: What Intel didn't tell you
Some high points of Intel's 45nm HKMG technology are: high-k first, metal-gate-last integration; hafnium oxide (HfO2) gate dielectric (1nm EOT); and dual band-edge work function metal gates (TiN for PMOS; TiAlN for NMOS). The gate-last integration is one point that needs a bit of clarification in the Intel process flow.
|2006-05-16||0.35μm CMOS process allows voltages from 3.3V to 120V
austriamicrosystems' Full Service Foundry business unit announced its 0.35μm high-voltage CMOS technology H35 with an additional set of 120V NMOS and PMOS devices.
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