What is design for manufacturability (DFM)?
| The design methodology called "design for manufacturability" (DFM) includes a set of techniques used to modify the design of semiconductors in order to make them more manufacturable by improving their functional yield, parametric yield, reliability etc. |
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| 2012-02-10 | Samsung, Cadence partner in nanometer SoC design The companies will collaborate on a design-for-manufacturing (DFM) infrastructure to tackle physical signoff and electrical variability optimization for 32, 28 and 20nm ICs. |
| 2011-05-12 | Cadence, TSMC team up to deliver DFM services Cadence, TSMC team up to deliver DFM services |
| 2011-02-11 | VIA adopts Mentor's Calibre PERC VIA Technologies has adopted Mentor Graphics's Calibre PERC electrical rule checking product for enabling ESD protection on its x86 processor platforms. |
| 2010-12-13 | Cadence, SMIC collaborate for 54nm SoC flow Semiconductor Manufacturing International Corp. has adopted Cadence's Encounter Digital Implementation System as the foundation for SMIC's Reference Flow 4.1. |
| 2010-12-06 | SMIC chooses Cadence for 65-nm reference flow Cadence Design Systems, Inc., has just announced that SMIC has adopted Cadence Silicon Realization products for the DFM and low-power technology at the center of SMIC's 65-nanometer Reference Flow 4.1. |
| 2010-08-27 | Magma Design Automation joins Si2's DFMC The coalition also announces a 60-day review period for the first release of OpenDFM, a high-level DRC language that can be translated into a variety of proprietary verification languages. |
| 2010-01-14 | Freescale taps Mentor test, verification tech The collaboration enables Freescale's deployment of Mentor's technologies to enhance design flows and methods. |
| 2009-07-31 | DAC panel revisits DFM debate DAC panel revisits DFM debate |
| 2009-03-24 | Process variability gets a second chance Mentor Graphics Corp. has a new message: process variability is not all bad. In fact, it could be considered a competitive advantage if properly dealt with, according to executives at the firm. |
| 2008-10-09 | TSMC, Mentor team on advanced physical verification TSMC and Mentor Graphics have collaborated on physical verification solutions leveraging a new feature of the Calibre nmDRC product called "Equation-Based DRC." |
| 2008-10-06 | Synopsys heralds 2-3x speed boost with IC Compiler release Claiming a 2X to 3X speed-up in overall design turnaround time compared to the previous release, Synopsys Inc. introduced last week the IC Compiler 2008.09. |
| 2008-08-27 | Cadence tool steps up IC package, SiP designs The release of SPB 16.2, due in November of this year, from Cadence Design Systems, delivers advanced IC package/system-in-package miniaturization, design cycle reduction and DFM-driven design, along with a new power integrity modeling solution. |
| 2008-08-26 | Despite Q2 loss, Mentor remains positive Mentor Graphics Corp. made a loss of $17.2 million on revenue of $182.4 million in Q2 ended July 31. |
| 2008-08-22 | Green trends heat up for next designs Gone are the days when design was, well, design. Today it's DFM, design-for-quality, design-for-cost and DfE. |
| 2008-08-01 | Looking beyond advanced design geometries With the presence of the design geometries between 1000nm and 1nm, we can start deploying 32nm flows and find the solutions of the transitional barriers between 32nm and 22nm. Design verification plays a vital role in reducing the design cost and improving the yield of the new products and product platforms. |
| 2008-07-23 | Is it all gloom for ATE? The shakeout in the automatic test equipment business is over. Or is it? |
| 2008-06-12 | Takumi teams up with quality design group Silicon recently announced that Takumi Technology has joined the Design-for-Manufacturability Coalition, which will build on previous efforts to ensure that ICs can be manufactured according to the original design intent. |
| 2008-06-12 | TSMC targets to unify 32nm design flow Facing the 32nm challenge, Taiwan Semiconductor Manufacturing Co. Ltd is putting the pedal to the metal with a new design-for-manufacturing scheme. |
| 2008-06-05 | TSMC stirs IC designs using 40nm node Paving the way for next-generation chips, TSMC is set to roll out its latest design methodology for IC production at the 40nm node. |
| 2008-05-27 | Assessing the DFM impact Assessing the DFM impact |
| 2008-05-01 | Sign-off smartly with SSTA At the 45nm process node, the SSTA approach to sign-off will allow designers to mitigate the effects of process variation, prevent silicon failures, and meet the demands of cutting-edge electronic design for the near future. It will usher in the much-anticipated "electrical DFM" that provides multi-objective placement, physical synthesis, and routing optimization while comprehending the full spectrum of physical and electrical implications of manufacturing. |
| 2008-03-18 | Synopsys, SMIC tip 90nm reference design flow Synopsys Inc. and SMIC have released an enhanced 90nm hierarchical, multivoltage RTL-to-GDSII reference design flow that benefits from advanced synthesis, design-for-test and DFM capabilities. |
| 2008-03-17 | Bring DFM/DFY into the routing engine Bring DFM/DFY into the routing engine |
| 2008-03-17 | Succeed at 65nm design A true DFM-aware environment accounts for process variability and lithographic effects in the context of timing, power, noise and yield at every stage of the flow. This begins with the characterization of the cell library, continues through implementation, analysis and optimization, and ends with sign-off verification. |
| 2008-01-02 | Expanding the DFM market Expanding the DFM market |
| 2007-09-24 | Magma, UMC deliver verification, DFM tools for 65nm Magma, UMC deliver verification, DFM tools for 65nm |
| 2007-09-21 | Firms join forces to advance DFM Firms join forces to advance DFM |
| 2007-09-17 | Avoid design snags with silicon contour predictor Designers can improve parametric yield and chip performance by accurately determining the impact of systematic variations during design. |
| 2007-08-21 | Cadence acquires DFM firm Clear Shape Cadence acquires DFM firm Clear Shape |
| 2007-08-01 | Follow a balanced DFx flow The best DFx flow available today combines the DFM-aware features in today's synthesis, placement and routing solutions with a post-route (pre-GDS) interconnect optimization step. |
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