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| 2009-07-31 |
DAC panel revisits DFM debate |
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Panelist revived the debate on design for manufacturing, with one executing calling it a 'band-aid with diminishing returns.' |
| 2008-08-27 |
Cadence tool steps up IC package, SiP designs |
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The release of SPB 16.2, due in November of this year, from Cadence Design Systems, delivers advanced IC package/system-in-package miniaturization, design cycle reduction and DFM-driven design, along with a new power integrity modeling solution |
| 2008-08-22 |
Green trends heat up for next designs |
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Gone are the days when design was, well, design. Today it's DFM, design-for-quality, design-for-cost and DfE |
| 2008-05-27 |
Assessing the DFM impact |
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The EDA industry, always looking for timely solutions to the existing problems of the electronics market, has taken the challenge of defining a new market segment. |
| 2008-05-01 |
Sign-off smartly with SSTA |
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At the 45nm process node, the SSTA approach to sign-off will allow designers to mitigate the effects of process variation, prevent silicon failures, and meet the demands of cutting-edge electronic design for the near future. It will usher in the much-anticipated "electrical DFM" that provides multi-objective placement, physical synthesis, and routing optimization while comprehending the full spectrum of physical and electrical implications of manufacturing |
| 2008-03-18 |
Synopsys, SMIC tip 90nm reference design flow |
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Synopsys Inc. and SMIC have released an enhanced 90nm hierarchical, multivoltage RTL-to-GDSII reference design flow that benefits from advanced synthesis, design-for-test and DFM capabilities |
| 2008-03-17 |
Bring DFM/DFY into the routing engine |
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In reality, DFM/DFY tools need to use a mixture of rules- and model-based techniques as appropriate. The solution is to bring DFM/DFY upstream into the design process; to create a design that is correct by construction; and to hand-off a design that is as manufacturing- and yield-friendly as possible |
| 2008-03-17 |
Succeed at 65nm design |
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A true DFM-aware environment accounts for process variability and lithographic effects in the context of timing, power, noise and yield at every stage of the flow. This begins with the characterization of the cell library, continues through implementation, analysis and optimization, and ends with sign-off verification |
| 2008-01-02 |
Expanding the DFM market |
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Apache's acquisition of Optimal is another clear signal that the EDA industry is adapting to provide designers with tools that allow them to work on the entire system, not just parts that have different physical characteristics. |
| 2007-09-24 |
Magma, UMC deliver verification, DFM tools for 65nm |
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Magma Design Automation Inc. has partnered with UMC to deliver a broad physical verification and design for manufacturability solution for 65nm designs. |
| 2007-09-21 |
Firms join forces to advance DFM |
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The Silicon Integration Initiative (Si2) announced that top chip makers and EDA tool vendors have established a design-for-manufacturing (DFM) coalition intended to build on previous DFM efforts |
| 2007-08-21 |
Cadence acquires DFM firm Clear Shape |
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Cadence Design has acquired Clear Shape Technologies, a design for manufacturing technology firm specializing in design-side solutions to minimize yield loss for advanced semiconductor ICs. |
| 2007-08-01 |
Follow a balanced DFx flow |
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The best DFx flow available today combines the DFM-aware features in today's synthesis, placement and routing solutions with a post-route (pre-GDS) interconnect optimization step |
| 2007-07-12 |
Cadence, STARC team to address 65nm DFM issues |
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Cadence and STARC have partnered to deliver an advanced design flow to address 65nm DFM issues |
| 2007-07-02 |
Manage design data effectively |
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Today's DFM process for electronic products typically includes a disparate range of disciplines. Hence, the task of coordinating the flow of information can be daunting. Here are some tips to implement effective data management |
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