Programmable Logic: [FPGAs/PLDs/Application Notes][Page 4] News, Tech Articles, App Notes

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Application Notes (Sorted By Date)

1:7 Deserialization in Spartan-3E FPGAs at speeds up to 666Mbps (2007-03-12)
Four- and six-layer, high-speed PCB design for the Spartan-3E FT256 BGA package (2007-03-12)
J drive: In-system programming of IEEE standard 1532 devices (2007-03-12)
DDR SDRAM controller using Virtex-4 FPGAs (2007-03-12)
Synthesizable CIO DDR RLDRAM II controller for Virtex-4 FPGAs (2007-03-12)

Xilinx video over IP solutions for Virtex-4 devices (2007-03-12)
Dual DIMM DDR2 SDRAM memory interface design guidelines (2007-03-05)
Stratix III power management design guide (2007-03-05)
Design guidelines for implementing DDR and DDR2 SDRAM interfaces in Stratix III devices (2007-03-05)
A flexible architecture to drive sharp two-way viewing angle and standard LCDs (2007-03-05)

Integrating uplink desubchannelization and ranging modules for WiMAX (2007-03-05)
Downlink subchannelization for WiMAX (2007-03-05)
Uplink desubchannelization for WiMAX (2007-03-05)
Design guidelines for implementing external memory interfaces in Stratix II and Stratix II GX devices (2007-03-05)
Configuring Xilinx FPGAs with SPI serial flash (2007-02-05)

0.18µm flash memory reprogramming in user boot mode (2007-02-05)
Rewriting flash memory in user program mode using asynchronous serial communication (2007-02-05)
Xilinx FPGA IFF copy protection with 1-Wire SHA-1 secure memories (2006-12-01)
JJ-20.11-compatible interface for the DS2155 and DS21455 SCTs (2006-06-02)
Power management controller for mixed-voltage FPGA based systems (2006-06-02)

Tips for successful power-up of today's high-performance FPGAs (2005-06-10)
Precision current source is software-programmable (2005-06-07)
Creating high-speed memory interfaces with Virtex-II and Virtex-II Pro FPGAs (2004-12-10)
FPGA interface to the TMSC6000 DSP platform using EMIF (2004-12-10)
Memory interface application notes overview (2004-12-10)

Configuring Xilinx FPGAs with SPI flash memories using CoolRunner-II CPLDs (2004-12-10)
Connecting Xilinx FPGAs to Texas Instruments ADS527x series ADCs (2004-12-10)
Reading user data from configuration PROMs (2004-12-10)
RocketIO X transceiver clock mode switcher for Virtex-II Pro X FPGAs (2004-12-10)
High-speed clock architecture for DDR designs using local inversion (2004-12-10)

PPC405 lockstep system on ML310 (2004-12-09)
Statistical profiler for embedded IBM PowerPC (2004-12-09)
Web server reference design using a PowerPC-based embedded system (2004-12-09)
SPI-4.2 to quad SPI-3 bridge (2004-12-09)
Implementing barrel shifters using multipliers (2004-12-09)

Analog devices TigerSHARC link (2004-12-09)
Clock and data recovery with coded data streams (2004-12-09)
Data Recovery (2004-12-09)
PCI bus target controller implementation using a Lattice CPLD (2003-12-20)
ORCA Series 4 I/O User's Guide (2002-12-11)

ORCA Series 3 FPGAs Programmable I/O Cell (PIC): Logic, Clocking, Routing, and External Device Interface (2002-12-11)
Boundary Scan Testability with Lattice's sysIO Capability (2002-12-11)
Supplemental Logic and Interconnect Cell (SLIC) ORCA Series 3 FGPAs (2002-12-06)
ORCA Series 4 Clocking Strategies (2002-12-06)
Metastability in MACH Devices (2002-12-06)

Benefits and advantages of SpeedLocking (2002-12-06)
ispLever starter kit (2002-12-06)
ORCA series 3 programmable clock manager (PCM) (2002-12-06)
ORCA series 3 to series 4 FPGA design conversion (2002-12-06)
ispLSI 5384VE application: High speed binary counter (2002-12-06)

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