Programmable Logic: [Programmable Logic/Application Notes][Page 5] News, Tech Articles, App Notes

Bits and Bytes

High-density FPGA handles 40G/100G apps
Altera Corp. has begun shipping what it claims to be the highest density, highest system-bandwidth FPGA to address the stringent demands of today's bandwidth-heavy applications.

Application Notes (Sorted By Date)

Philips PLDs support live insertion applications (2001-05-25)
Pad pieces (2001-04-23)
On-chip pull-up/Pull-down resistors (2001-04-23)
Metastability (2001-04-23)
Using SelectI/O interfaces in Spartan-II FPGAs (2001-04-12)

High-speed FIFOs in Spartan-II FPGAs (2001-04-12)
Virtex series configuration architecture user guide (2001-04-12)
Using FPGAs as a flexible PCI interface solution (2001-04-12)
The behavior of integrated bus hold circuits (2001-04-06)
Thermal considerations for FAST logic products (2001-04-06)

PLS173 as a 10-bit comparator, 74LS460 (2001-04-04)
Latches and flip-flops with PLS153 (2001-04-04)
Understanding the Warp report file for Ultra37000-devices (2001-03-30)
Design optimization using Warp synthesis directives (2001-03-30)
State machine design considerations and methodologies (2001-03-28)

PCI target designs using Ultra37000 CPLDs (2001-03-27)
Are your PLDs metastable? (2001-03-27)
Designing with Cypress in-system reprogrammable (ISR) CPLDs for PC cable programming (2001-03-23)
Using Cypress CPLDs in mixed-voltage systems (2001-03-23)
Board layout considerations for ISR programming of Cypress CPLDs (2001-03-23)

An introduction to in-system reprogramming with FLASH370i (2001-03-23)
Cascading ISR devices (2001-03-23)
Using the Ultra37000 ISR prototype board (2001-03-23)
Using the Delta39K ISR prototype board (2001-03-23)
The Delta39K/Quantum38K carry chain (2001-03-21)

Delta39K PLL and clock tree (2001-03-21)
Configuring Delta39K/Quantum38K (2001-03-21)
Understanding bus-hold: A feature of Cypress CPLDs (2001-03-21)
FIFO Dipstick using Warp2 VHDL and the CY7C371 (2001-03-21)
ISR programming using an embedded processor with Jam (2001-03-21)

Efficient arithmetic designs with Cypress CPLDs (2001-03-21)
ECL outputs (2001-03-20)
The FLASH370i family of CPLDs and designing with Warp2 (2001-03-19)
Designing with the CY7C335 and Warp2 VHDL compiler (2001-03-19)
FLASH370i 5V to 12V dc-dc converter solutions (2001-03-19)

CPLD power consumption comparison (2001-03-19)
Converting designs from FLASH370i to Ultra37000 devices (2001-03-19)
An introduction to in-system reprogramming (ISR) with the Ultra37000 (2001-03-19)
Battery-powered 5MHz frequency counter (2000-12-12)
An MSI 500MHz frequency counter using MECL and MTTL (2000-12-12)

NBCD sign and magnitude adder/subtracter (2000-12-12)
Understanding MECL 10,000 DC and AC data sheet specifications (2000-12-12)
Interfacing with MECL 10,000 Integrated Circuits (2000-12-11)
Bussing with MECL 10,000 Integrated Circuits (2000-12-11)
ECLinPS, ECLinPS lite and ECLinPS plus device type and date code marking guide (2000-12-11)

EPT SPICE modeling kit (2000-12-08)
The ECL translator guide (2000-12-08)
ECLinPS Lite MC100LVELT22 SPICE model kit (2000-12-08)
H124, 125, 350-352 translator I/O SPICE modeling kit (2000-12-07)
Board and interface design for AutoBahn Spanceiver (MC100SX1451FI50/100) (2000-12-07)

366 Records, Total 8 Page, The 5 Page

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