Application Notes (Sorted By Date)
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Bus-Structured Serial Input/Output Device
(2000-06-26)
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hongkong@xilinx.com
(2000-06-26)
-
Using the Virtex delay-locked loop
(2000-06-26)
-
170MHz FIFOs Using the Virtex Block SelectRAM+
(2000-06-26)
-
System design with new XC4000X I/O features
(2000-06-26)
-
XC4000 series technical information
(2000-06-26)
-
Using the XC4000 readback capability
(2000-06-23)
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Configuring mixed FPGA daisy chains
(2000-06-23)
-
Building high performance FIR filters using KCMs
(2000-06-23)
-
16-Tap, 8-Bit FIR filter applications guide
(2000-06-22)
-
Implementing state machines in LCA devices
(2000-06-22)
-
Ultra-fast synchronous counters
(2000-06-22)
-
Estimating the performance of XC4000E adders and counters
(2000-06-22)
-
Accelerating loadable counters in XC4000
(2000-06-22)
-
Using the dedicated carry logic in XC4000E
(2000-06-22)
-
Using the Virtex SelectIO
(2000-06-21)
-
Using manual power down mode with SpartanXL FPGAs
(2000-06-21)
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Conserving power with auto power down mode in SpartanXL FPGAs
(2000-06-21)
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Virtex power estimator user guide
(2000-06-21)
-
The express configuration of SpartanXL FPGAs
(2000-06-21)
-
The low-cost, efficient serial configuration of Spartan FPGAs
(2000-06-21)
-
Using three-state enable registers in XLA, XV, and SpartanXL FPGAs
(2000-06-21)
-
How Spartan series FPGAs compete for gate array production
(2000-06-20)
-
I/O characteristics of the 'XL FPGAs
(2000-06-20)
-
PLD Replacement
(2000-05-30)
-
PLD software tools overview
(2000-03-29)
-
FLEX script programmer's guide
(2000-03-06)
-
Surface-Mount IC packages
(2000-03-01)
-
The PowerPAD Thermally Enhanced Package
(2000-02-29)
-
Hot-swappable capabilities of Actel's SX-A and SX FPGAs
(2000-02-29)
-
An Introduction to Active-HDL Sim
(2000-02-22)
-
Timing-Driven Flow (TDF) SLI ASIC design flow with commercial EDA tools
(2000-02-11)
-
A programmable logic array design
(1999-12-25)
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EMI/RFI board design
(1999-12-24)
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General guidelines used for PCB design for V3 Semiconductor evaluation boards
(1999-12-23)
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CPLD schematic design guide
(1999-12-22)
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Adapting ASIC designs for use with Spartan FPGAs
(1999-12-21)
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OrCAD Express design flow for Philips CPLDs
(1999-11-23)
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Metastable Recovery
(1999-10-09)
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Are your PLDs metastable?
(1999-10-08)
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