Application Notes (Sorted By Date)
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SPECCTRA V9.0 node locked installation for Windows
(2001-05-29)
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The exception file in PDIF file reader
(2001-05-29)
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Database version and master designer version
(2001-05-29)
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Creating an edge connector as a through-hole part
(2001-05-29)
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Creating non-homogeneous parts and symbols
(2001-05-29)
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Adding pins to an existing part file using PDIF
(2001-05-28)
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Using and understanding ports
(2001-05-28)
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Storing a view
(2001-05-28)
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Removing ERC and DRC error indicators
(2001-05-28)
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Importing text from a file into ACCEL SCH or PCB
(2001-05-28)
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Library creation from ACCEL ASCII netlist
(2001-05-28)
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Displaying alternate views of a symbol
(2001-05-28)
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ACCEL-To-SPECCTRA interface and design language translation
(2001-05-28)
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Loading control characters in ACCEL EDA
(2001-05-28)
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Hierarchical hints
(2001-05-28)
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Performing engineering change orders (ECOs)
(2001-05-28)
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One pin representation to multiple pads
(2001-05-28)
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Using Multibit register inference to save area and power
(2001-05-24)
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Using formality for RTL-to-gate in LSI Logic's FlexStream design flow
(2001-05-24)
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Using PrimeTime in LSI Logic's FlexStream design flow
(2001-05-24)
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Using formality in LSI Logic's FlexStream design flow
(2001-05-24)
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Periodic s-parameter and noise analysis using SpectreRF PSP/PNOISE analyses
(2001-04-26)
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Modeling and application of bonding pads
(2001-04-26)
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Accurate Fourier analysis for circuit simulators
(2001-04-26)
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An introduction to the PLL library
(2001-04-26)
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Oscillator noise analysis in SpectreRF
(2001-04-26)
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Synthesizing LSS designs with Synopsys design compiler
(2001-04-25)
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How to simulate RTL designs with LSS memory
(2001-04-25)
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Boundary scan and internal scan
(2001-04-23)
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Clocking at AMI
(2001-04-23)
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Guidelines for supplying test vector simulations
(2001-04-23)
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Using NAND tree test circuits for input parametric testing
(2001-04-23)
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Varactor SPICE models for RF VCO applications
(2001-04-19)
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Data generation and configuration for Spartan series FPGAs
(2001-04-12)
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Importing a Warp post-fit netlist into Mentor Graphics' ModelSim
(2001-03-30)
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Targeting Cypress PLDs from the Synopsys FPGA Express environment
(2001-03-29)
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Software considerations for the VIC64
(2001-03-28)
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An introduction to active-HDL Sim
(2001-03-28)
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Targeting Cypress PLDs from the Leonardo Spectrum Environment
(2001-03-26)
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Using IEEE 1149.1 boundary scan (JTAG) with Cypress Ultra37000 CPLDs
(2001-03-23)
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An Introduction to active-HDL FSM
(2001-03-22)
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Using hierarchy in VHDL design
(2001-03-22)
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Method to instantiate and use a core in Warp Enterprise/Professional
(2001-03-21)
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Getting started converting .ABL files to VHDL
(2001-03-20)
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Abel-HDL vs. IEEE-1076 VHDL
(2001-03-20)
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Targeting Cypress PLDs from the Cadence environment
(2001-03-20)
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Method to instantiate and use a core in LeonardoSpectrum
(2001-03-20)
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Method to instantiate and use a core in Warp with Cypress CPLDs
(2001-03-20)
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Method to instantiate and use a core in Synplify
(2001-03-20)
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MC10/100H600 translator family I/O SPICE modeling kit
(2000-12-06)
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