EDA/IC Design: [EDA/Application Notes][Page 6] News, Technical Archives, App Notes

Market Watch

Outsourced IC design growth slowed 20% in '08
2009 will be a make or break year for chip design service providers after the recession slowed the growth of outsourced chip design starts last year, according to a survey by Gartner Inc.

Application Notes (Sorted By Date)

Component pin code convention (2001-05-29)
How to clear Flash (2001-05-29)
Hierarchical hints (2001-05-28)
Performing engineering change orders (ECOs) (2001-05-28)
Loading control characters in ACCEL EDA (2001-05-28)

One pin representation to multiple pads (2001-05-28)
ACCEL-To-SPECCTRA interface and design language translation (2001-05-28)
Importing text from a file into ACCEL SCH or PCB (2001-05-28)
Removing ERC and DRC error indicators (2001-05-28)
Library creation from ACCEL ASCII netlist (2001-05-28)

Displaying alternate views of a symbol (2001-05-28)
Storing a view (2001-05-28)
Using and understanding ports (2001-05-28)
Adding pins to an existing part file using PDIF (2001-05-28)
Using PrimeTime in LSI Logic's FlexStream design flow (2001-05-24)

Using formality in LSI Logic's FlexStream design flow (2001-05-24)
Using formality for RTL-to-gate in LSI Logic's FlexStream design flow (2001-05-24)
Using Multibit register inference to save area and power (2001-05-24)
An introduction to the PLL library (2001-04-26)
Oscillator noise analysis in SpectreRF (2001-04-26)

Accurate Fourier analysis for circuit simulators (2001-04-26)
Modeling and application of bonding pads (2001-04-26)
Periodic s-parameter and noise analysis using SpectreRF PSP/PNOISE analyses (2001-04-26)
How to simulate RTL designs with LSS memory (2001-04-25)
Synthesizing LSS designs with Synopsys design compiler (2001-04-25)

Guidelines for supplying test vector simulations (2001-04-23)
Using NAND tree test circuits for input parametric testing (2001-04-23)
Clocking at AMI (2001-04-23)
Boundary scan and internal scan (2001-04-23)
Varactor SPICE models for RF VCO applications (2001-04-19)

Data generation and configuration for Spartan series FPGAs (2001-04-12)
Importing a Warp post-fit netlist into Mentor Graphics' ModelSim (2001-03-30)
Targeting Cypress PLDs from the Synopsys FPGA Express environment (2001-03-29)
An introduction to active-HDL Sim (2001-03-28)
Software considerations for the VIC64 (2001-03-28)

Targeting Cypress PLDs from the Leonardo Spectrum Environment (2001-03-26)
Using IEEE 1149.1 boundary scan (JTAG) with Cypress Ultra37000 CPLDs (2001-03-23)
Using hierarchy in VHDL design (2001-03-22)
An Introduction to active-HDL FSM (2001-03-22)
Method to instantiate and use a core in Warp Enterprise/Professional (2001-03-21)

Method to instantiate and use a core in Warp with Cypress CPLDs (2001-03-20)
Method to instantiate and use a core in Synplify (2001-03-20)
Method to instantiate and use a core in LeonardoSpectrum (2001-03-20)
Targeting Cypress PLDs from the Cadence environment (2001-03-20)
Abel-HDL vs. IEEE-1076 VHDL (2001-03-20)

Getting started converting .ABL files to VHDL (2001-03-20)
MC10/100H600 translator family I/O SPICE modeling kit (2000-12-06)
FACT I/O model kit (2000-12-05)
Testpoints (2000-12-04)
Stub length (2000-12-04)

342 Records, Total 7 Page, The 6 Page

Article review

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