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Bits and bytes
New Products (Sorted By Date)
- EverCAD platform suits mixed-signal SoC design (2004-08-09)
- French EDA startup targets custom designers (2004-08-05)
- IDT rolls out Linux 2.6 offering (2004-08-03)
- Pentek VIM-2 module eyes compute-intensive engines (2004-07-28)
- AWR, TSMC team up for SiGe design platform (2004-07-28)
- Assembléon verification software provides comprehensive facilities (2004-07-27)
- Cadence announces latest Allegro platform (2004-07-26)
- Mentor tool links FPGA, PCB design (2004-07-23)
- Bustronic offers 32-bit cPCI backplanes (2004-07-22)
- Mentor Graphics releases tools for systems with 64-bit Linux (2004-07-19)
- Consultant creates low-end mixed-signal simulator (2004-07-16)
- Evaluator board jump-starts PFC designs (2004-07-15)
- MIPS hard IP cores help reduce design time (2004-07-15)
- Collaboration to develop ultra-thin gate-insulation layers (2004-07-15)
- AutoVue adds PCB manufacturability analysis (2004-07-13)
- Mentor announces support for SMIC mixed-signal process (2004-07-12)
- Adeset rolls out BSP for Atmel MCU (2004-07-09)
- Altera's updated FPGA tool suggests optimizations (2004-07-09)
- Shenzhen Fast-print PCBs feature 0.09mm line space (2004-07-01)
- Low-cost FPGAs readied for launch (2004-07-01)
- TI pushes the limits of low power in three DSPs (2004-07-01)
- Altium new design system released to beta testing (2004-06-30)
- ProDesign expands hardware-assisted platform line (2004-06-30)
- Safelogic rolls out new property checking solution (2004-06-30)
- Fast-print PCBs offer 0.9mm thickness (2004-06-30)
- Agilent connectorless logic analyzer adopted as standard (2004-06-29)
- Monterey new technology reduces SoCs' die size (2004-06-17)
- Synopsys low-power solution supports 90nm designs (2004-06-17)
- Xilinx unveils multiplatform FPGAs (2004-06-16)
- NEC engineers advance HW/SW co-verification (2004-06-16)
- Synopsys IC, SoC tool reduces design time, cost (2004-06-15)
- Silvaco rollout includes mixed-signal simulation (2004-06-10)
- TriQuint rolls out ADS kits for pHEMT processes (2004-06-10)
- Incentia releases runtime QOR for tool line (2004-06-09)
- Atmel rolls out development kits for UHF ICs (2004-06-09)
- Xilinx releases latest version of System Generator (2004-06-09)
- 0-In tools support Accellera SystemVerilog 3.1a (2004-06-08)
- Synopsys adds RF engine to HSPICE (2004-06-08)
- TSMC Reference Flow 5.0 includes Optimal tools (2004-06-07)
- Adveda modeler connects RTL, SystemC simulation (2004-06-03)
- Silvaco offers full-chip RC extraction (2004-06-03)
- TransEDA releases new code coverage tools (2004-06-02)
- Synopsys adds testbench features to VCS (2004-06-01)
- Startup offers new 'route' to IC design (2004-06-01)
- Prolific offers tool to assure signal integrity (2004-06-01)
- EDA startup preps tools for RTL closure (2004-06-01)
- Adveda launches extension to RTL simulator (2004-06-01)
- Electech PCBs have 610-by-460 board size (2004-05-27)
- Accelerated Tech develops RTOS for Altera Nios II (2004-05-25)
- CriticalBlue releases coprocessor synthesis tool (2004-05-24)
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