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Bits and bytes
News & Trends (Sorted By Date)
- Design challenges and sign-off criteria in nanometer era (2003-09-16)
- SVP is key technology for nanometer IC design (2003-09-16)
- Redefining design for yield, manufacturability (2003-09-16)
- SynTest appoints Logicad as distributor in India (2003-09-15)
- Researchers reflect on maskless lithos (2003-09-11)
- CoWare fills advisory panel with chip-design notables (2003-09-08)
- Doulos, ARM team on platform verification course (2003-09-08)
- Integre joins Tower Semiconductor design program (2003-09-05)
- 11th EDA&T-Hsinchu to highlight design chain issues, market opportunities (2003-09-05)
- Circuit Semantics lands additional venture funding (2003-09-04)
- Kemet enters alliance with Lamina Ceramics (2003-09-04)
- Chartered announces 0.13µm production ramp (2003-09-03)
- Startup eyes hard/software pre-silicon validation (2003-09-03)
- Cadence brings 0.5µm design kit to China (2003-09-02)
- Recovery of semiconductor industry on track: Gartner (2003-09-02)
- Ansoft carves another niche for HFSS tool (2003-09-01)
- Fresh crop of EDA startups (2003-09-01)
- Faraday to expand IP cores with UMC process (2003-08-29)
- 0-In Design obtains patent in assertion-based verification (2003-08-28)
- Tower Semiconductor obtains $2.5M in investments (2003-08-26)
- TransEDA proposes asset sale to Valiosys (2003-08-26)
- Unaxis consolidates divisions, forms new company (2003-08-22)
- Pure-play foundry growth expected to soar (2003-08-22)
- Startup turns to China for analog design suite (2003-08-19)
- Cadence platforms adopted by China-based IC design center (2003-08-15)
- Peritek acquired by mil-aero supplier (2003-08-15)
- Kawasaki Micro, CoreSim collaborate on ASIC OEM service (2003-08-14)
- Cadence raising $350M for possible acquisition (2003-08-13)
- Designers gravitate toward RTL sign-off (2003-08-13)
- Silicon Metrics wins key patent (2003-08-12)
- Averant lands patent for checking design properties (2003-08-12)
- Cadence announces second Asia technology symposium (2003-08-11)
- TransChip adopts Nassda simulator (2003-08-11)
- Aspex adopts Cadence solutions (2003-08-08)
- Averant lands patent for checking design properties (2003-08-08)
- RTL tool provider snags $5.3M funding (2003-08-07)
- Sanmina-SCI, Tellabs expand outsourcing agreement (2003-08-07)
- PalmChip bus patent threatens most SoCs (2003-08-06)
- Mentor debt sale may fuel acquisitions (2003-08-05)
- Cadence platform to be deployed by Global Unichip (2003-08-04)
- Unifying ESL, verification (2003-08-01)
- Coexistence in a multilingual design world (2003-08-01)
- Design-for-test moves up to RT level (2003-08-01)
- Cookson restructures product portfolio (2003-07-31)
- Mentor signs Memec to distribute Inventra IPs (2003-07-31)
- NEC sets Agilent tools as RFIC design standard (2003-07-30)
- Verplex upgrades formal-verification line (2003-07-30)
- Outsourcing services put chip designers on edge (2003-07-29)
- Agilent taps startup's Verilog-A compiler (2003-07-28)
- Cree acquires silicon carbide patents from ABB (2003-07-28)
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Top Ranked Articles
- Wafer-level packaging achieves prominence
- Confab to highlight nanotech for bio
- Comment: Gphones should be more open in net search
- IBM transits to 45nm SOI
- IPO candidates await market recovery
- VC funding for chip firms slows down
- Bozotti cites key points for ST's rehabilitation
- LCD TV design solution achieves 90% efficiency
- Intel to showcase 32nm technology at confab
- GooglePhone responds to Android's aspirations
