|
Just as power consumption has a cascading effect, from the component level to the application level, so does power-wise design intent, from IC to systems design. |
Power down with power-wise design
By Vivek Nanda The new UN report on climate change published early February thrust a grim and grimy reality into humanity's face. Although politicians reportedly got the scientists to delete some of the timelines for forecast events and decrease the level of confidence in projections just hours before it was released, the report is still a wake-up call for consumers, industry and policy makers alike in that it places the blame for global warming squarely on human activity. The scientists concluded that if carbon dioxide concentrations in the atmosphere were to reach twice their pre-industrial levels, the global climate could warm by 3.5°C to 8°C by the turn of the century. There is over a 10 percent chance of much greater warming. Sea levels could rise by 3.7m to 6.1m. The buildup of carbon dioxide could decrease the pH level of sea water, which could wipe out some kinds of corals and plankton that feed or house other marine life. Much of the pollution comes from our power-hungry lifestyle and products. No wonder then that Al Gore delivered his message on saving the environment to embedded systems designers gathered at the Embedded Systems Conference in San Jose on April 2. Gore called for embedded designers to apply "moral authority" to their designs and challenged them to develop architectures that aim for efficiency and conservation. Although not an engineer, Gore had prepared well—he even asked for parallel processing to increase computing efficiencies. Many engineers have already lent their expertise and effort to increasing power efficiency, and several announcements have recently been made about technologies and products that help reduce power consumption. In April, IBM announced that it had developed a way to attach multiple die by using vertical connections etched through silicon wafer and filled with metal. The technique could improve power efficiency in SiGe-based wireless products by 40 percent or in multicore CPUs by 20 percent. In February's International Solid-State Circuits Conference, researchers from the University of Bologna, STMicroelectronics and Fraunhofer IZM jointly described a 3D integration of chips using interconnection based on capacitive coupling. Their chip enabled vertical propagation of a 1.7GHz clock, a propagation delay of 420ps and throughput of 22Mbps/µm² with energy consumption of 0.08pJ/bit. Japan's Keio University and the University of Tokyo have developed a 90nm CMOS transceiver for inductive coupling. At a data rate of 1Gbps, its overall energy dissipation is 20 times lower than anything previously published. France-based CEA/Leti has come up with an architecture for a modular IC that harvests thermal energy and stores power in the microwatt range. The unit includes two micropower sources and an associated management IC. A microbattery is deposited above the IC in a 30mm² space to store the power. Researchers at the Massachusetts Institute of Technology have developed an energy-minimization loop that can dynamically track the minimum-energy operating voltage of a digital circuit. The DC/DC converter that enables such operation can achieve over 80 percent efficiency while delivering load powers of 1µW and higher from a 1.2V supply. Meanwhile, a team of researchers at Lawrence Berkeley National Laboratory is working on proposing new power standards and practices for large network switches, wireless access points, STBs, home-control systems and other consumer gear as part of a two-year effort. In line with this, the group will propose a new proxy feature that an NIC could use to maintain a PC's presence on the Net while the computer goes into sleep mode. As new power-reducing technologies and design methodologies rapidly emerge to help you power your products down and cut waste, the Embedded Systems Conference-Taiwan (ESC-Taiwan)—to be held August 23-24 in Taipei—will host a discussion on this relevant and timely issue. Just as power consumption has a cascading effect, from the component level to the application level, so does power-wise design intent, from IC design to systems design. The discussion at the ESC-Taiwan will similarly consider the power problem from these angles. You are all invited to attend.
|
| ||||||||||
| ||||||||||







