Design complexity continues to increase, as always, along with demand for smaller, lighter consumer equipment that runs longer on batteries. The CE market is also driven by continual enhancement of device feature sets.

With each device generation, pressures on system and board design engineers are eventually passed on to the IC vendor. The vendors move IC design and manufacturing from node to smaller node in an effort to realize smaller chip sizes, greater functionality, higher performance and lower power consumption at reduced costs.

For example, vendors can increase IC performance by about 20 percent simply by moving the design from 90nm to 65nm, while achieving twice as much circuit density. An IC at 45nm is expected to consume 25 percent the power it guzzles at 90nm.

The migration to ever finer processes becomes even more attractive, as new device characteristics often enable new applications. For instance, a move toward 100GbE will require such performance from enabling ICs that some of them may need to be manufactured at the 65nm node, since it will allow I/O signaling speeds up to 10Gbps.

When we moved to the 130nm node, the industry migrated from aluminum interconnects to copper. Design rule changes were required among other things in the design and process flows. The new metal came with its own issues: Copper formed voids in vias when stressed so that deposition and annealing techniques had to be suitably optimized.

We are now making ICs with the minimum feature size measuring 90nm. This node was enabled by more breakthroughs in new low-k dielectrics, which unfortunately have lower mechanical strength and higher coefficient of thermal expansion. Engineers had to learn to work with yet another revision to their DRC manual.

Just as we've begun accepting 90nm into the mainstream of design, several companies are ramping up 65nm production this year and design at this node is likely to see wider adoption over the next couple of years. Companies like Texas Instruments and STMicroelectronics have announced their own road maps leading to 45nm and beyond.

Process challenges up to 45nm will be solved not just by new materials, but by innovative lithography techniques. Immersion lithography will give optical scanner technology a new lease on life. The image coupling wavelength (that between the lens and the resist) can be reduced by using a fluid with a refractive index higher than one. TI for one announced in June that they will use 193nm photolithography to see their products through 45nm and 32nm nodes.

All this progress in production technology requires you to build bigger and more complex circuits necessitating design-for- manufacture (DFM) techniques for maintaining acceptable yield. Tools for multinode optimization up to the 45nm node are now emerging from smaller companies like Sierra Design Automation.

But beyond that, mere optimization of layout for a particular node may not work. A restrictive design rules (RDR) methodology, which is reportedly being explored by four to five large IDMs such as IBM and Intel, is poised to disrupt the way you design ICs. The idea is to set bounds within which EDA tools will generate layouts that are fabrication-aware.

The next breakthrough is not likely to be a new production technology, but one driven by EDA tools. The burning question is how much design gap EDA vendors will allow before they tackle the old ASIC methodology and drive growth in IC CAD tools.

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