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16 September 2006
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News & Analysis
With PCB designs getting faster and more complicated, designers are starting to fret about signal integrity, thermal issues and EMI. But respondents to the PCB portion of the EE Times 2006 EDA Users Survey said that meeting cost budgets is their greatest concern.
Freescale Semiconductor is stepping up its wireless push, armed with innovations in magnetoresistive memory and packaging, and guided by a new general manager, Sandeep Chennakeshu, recruited from Ericsson's handset group.
Any EDA vendor or large EDA user will tell you there's a compelling need for a standard way to express power-management intent throughout the IC design flow. The problem is that two separate groups are working toward that objective, amid profound disagreements over how to get there.
Tapping a new display technology, Motorola's 9mm-thick Motofone uses an electrophoretic display—an ultrathin, low-power display often referred to as electronic paper.
National Instruments recently launched LabVIEW 8.20, extending the popular graphical programming platform with communications design and simulation test tools for telecom design and test engineers.
Top developers of soft switches and IP multimedia subsystems have expanded their systems to add high availability and true fault tolerance to Session Initiation Protocol-based packet networks.
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HDD and NAND flash vendors have agreed on a peaceful coexistence, claiming that the two technologies are complementary and emphasizing the need to select the one most appropriate for a particular application.
There's growing evidence showing that U.S. chip design is becoming more vulnerable to offshoring in places like China and India—a scenario that has long troubled the minds of U.S. engineers.
Analog Devices Inc. spin-off On Demand Microelectronics AG is embarking on an aggressive IP strategy to bring new programmable solutions for multimedia applications currently done in hardware.
Ikanos Communications has unveiled its fifth generation of VDSL/ADSL chipsets in anticipation of the rapid growth in IPTV services.
Berkeley Design Automation has released FastSpice and RF FastSpice, which claim to speed Spice simulation by five- to tenfold while preserving full Spice accuracy.
Fourth-generation release of Linux aims at networking equipment and handheld devices including cellphones.
F5 Networks has integrated Swan Labs' Web acceleration tools into its own Traffic Management Operating System environment.
Averant has rolled out the next generation of its Solidify tool, offering designers fine control over the thoroughness of formal verification.
MPC8572 boasts full deflation engines and pattern-matching engines that allow it to perform seven-layer processing tasks.
Designers who have completed 65nm projects point to leakage current as the biggest problem, and they're turning to a variety of strategies to manage power.
EDA leaders are recognizing the need to work at higher levels of abstraction to create design files that generate both the hardware and software needed.
The complexity of the SI challenge has brought to fore three SI analysis disciplines—IR drop analysis, functional noise analysis and the analysis of noise's effect on timing.
Here are protection mechanisms that designers and companies can adopt to lessen the risk of IP loss when offshoring.
Learn how to successfully integrate ESL modules with existing RTL IP.
Recent developments in Europe may challenge the United States' dominance of the microelectronics industry in years to come.
Technical Features
32bit MCUs are providing high-performance and cost-effective solutions for home appliances, white goods, CE products and other applications. (PDF file)
B3G is not about creating a new ruling technology—it is a concept of a network of networks where all existing technologies are supported. (PDF file)
This article discusses several simple steps you can take to achieve a high-quality audio input solution when embedding microphones for laptops. (PDF file)
Find out how the load transient boost technology solves all AD contributions and cancels Tsr. (PDF file)
DFM methodologies such as RRA and CAA, combined with traditional DRC and accurate fab yield impact data, help designers determine whether design modifications actually result in higher-yielding silicon. (PDF file)
LVDS buffers can isolate impedance discontinuities to reduce system costs and enhance interface performance. (PDF file)
By improving the architecture of a non-PCI Ethernet controller, designers can improve overall system performance in consumer electronics, entertainment A/V, and home network designs. (PDF file)
Various automated tools makes the development of FPGA-based DSP systems faster and easier than ever before. (PDF file)
Flexibility in fuel-cell systems requires a flexible approach to testing them for secure, long-term development. (PDF file)
Opinion
The last two decades have seen the emergence of a vibrant Asian electronics business environment due to the electronics engineer.
Mentor Graphics CEO Wally Rhines says that since the inception of the EDA industry, innovation has evolved from and thrived within both large companies and small startups.
Interview
Cadence Design Systems Inc. senior VP and CTO, Ted Vucurevich, sat down recently with EE Times' Richard Goering and discussed developments ranging from new CAD architectures to EDA tools for nanotechnology-based systems like labs-on-a-chip.
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