( File format: PDF, 379 KB )
USB Streaming Controller (STC)
The TUSB3200A integrated circuit (IC) is a universal serial bus (USB) peripheral interface device designed specifically for applications that require isochronous data streaming. Applications include digital speakers, which require the streaming of digital audio data between the host PC and the speaker system via the USB connection. The TUSB3200A device is fully compatible with the USB Specification Version 1.1 and the USB Audio Class Specification. The TUSB3200A uses a standard 8052 microcontroller unit (MCU) core with on-chip memory. The MCU memory includes 4K bytes of program memory ROM that contains a boot loader program. At initialization, the boot loader program downloads the application program code to an 8K RAM from a nonvolatile memory on the printed-circuit board (PCB). The MCU handles all USB control, interrupt and bulk endpoint transactions. In addition, the MCU can handle USB isochronous endpoint transactions. The USB interface includes an integrated transceiver that supports 12 Mb/s (full speed) data transfers. In addition to the USB control endpoint, support is provided for up to seven in endpoints and seven out endpoints. The USB endpoints are fully configurable by the MCU application code using a set of endpoint configuration blocks that reside in on-chip RAM. All USB data transfer types are supported. The TUSB3200A device also includes a codec port interface (C-Port) that can be configured to support several industry standard serial interface protocols. These protocols include the audio codec (AC) ?97 Revision 1.X, the audio codec (AC) ?97 Revision 2.X and several Inter-IC sound (I2S) modes. A direct memory access (DMA) controller with four channels is provided for streaming the USB isochronous data packets to/from the codec port interface. Each DMA channel can support one USB isochronous endpoint. An on-chip phase lock loop (PLL) and adaptive clock generator (ACG) provide support for the USB synchronization modes, which include asynchronous, synchronous and adaptive. Other on-chip MCU peripherals include an Inter-IC control (I2C) serial interface, two general-purpose input/output (GPIO) ports, and a pulse width modulation (PWM) output. The TUSB3200A device is implemented in a 3.3-V 0.25 um CMOS technology. In addition, the use of 5-V compatible input/output buffers for the codec port interface allows the TUSB3200A device to be connected to either 3.3-V or 5-V codec devices.
Universal Serial Bus (USB) USB Specification version 1.1 compatible USB Audio Class Specification 1.0 compatible Integrated USB transceiver Supports 12 Mb/s data rate (full speed) Supports suspend/resume and remote wake-up Supports control, interrupt, bulk and isochronous data transfer types Supports up to a total of 7 in endpoints and 7 out endpoints in addition to the control endpoint Data transfer type, data buffer size, single or double buffering is programmable for each endpoint On-chip adaptive clock generator (ACG) supports asynchronous, synchronous and adaptive synchronization modes for isochronous endpoints To support synchronization for streaming USB audio data, the ACG can be used to generate the master clock for the codec Micro-Controller Unit (MCU) Standard 8052 8-bit core 4K Bytes of program memory ROM that contains a boot loader program that loads the application firmware from external EEPROM 8K Bytes of program memory RAM which is loaded by the boot loader program 256 Bytes of internal data memory RAM Two GPIO ports MCU handles all USB control, interrupt and bulk endpoint transfers DMA Controller Four DMA channels to support streaming USB audio data to/from the codec port interface Each channel can support a single USB isochronous endpoint For I2S modes, either a single or multiple USB isochronous endpoints can be used to support multiple DACs/ADCs Codec Port Interface Configurable to support AC?97 1.X, AC?97 2.X or I2S serial interface formats I2S modes can support a combination of up to 4 DACs and/or 3 ADCs Can be configured as a general-purpose serial interface I2C Interface Master only interface Does not support a multimaster bus environment Programmable to 100 kbit/s or 400 kbit/s data transfer speeds Pulse Width Modulation (PWM) Output Programmable frequency range from 732.4 Hz to 93.75 kHz Programmable duty cycle General Characteristics Available in a 52-Pin TQFP Package On-chip phase-locked loop (PLL) with internal oscillator is used to generate internal clocks from a 6 MHz crystal input 3.3-V core and 5-V compatible input/output buffers used for codec port interface Reset output available which is asserted for both system and USB reset External MCU mode supports application firmware development