2Mbps, Single Pair HDSL Analog Front End
Texas Instruments
Description
Burr-Brown's Analog Front End greatly reduces the size and cost of a single pair HDSL (High bit rate Digital Subscriber Line) system by providing all of the active analog circuitry needed to connect an HDSL digital signal processor to an external compromise hybrid and an HDSL line transformer. The transmit and receive filter responses automatically change with clock frequency, allowing the AFE1205 to operate over a wide range of data rates. The power dissipation of the device can be reduced under digital control for operation at lower speeds. The AFE1205 will operate at bit rates from 160kbps to 2.3Mbps. It meets ETSI PSD specifications for single pair E1, as well as ETSI and ANSI PSD specifications for two pair E1 and T1.Functionally, this unit consists of a transmit and a receive section. The transmit section generates, filters, and buffers outgoing 2B1Q data. The receive section filters and digitizes the symbol data received on the telephone line. This IC operates on a single 5V supply. The digital circuitry in the unit can be connected to a supply from 3.3V to 5V. The chip uses only 385mW for full-speed operation. It is housed in a small 48-lead SSOP package.The receive channel is designed around a fourth-order delta-sigma analog-to-digital converter. It includes a difference amplifier designed to be used with an external compromise hybrid for first-order analog echo cancellation. A programmable gain amplifier with gains 0dB to +9dB is also included. The delta-sigma modulator, operating at a 24X oversampling ratio, produces a 14-bit output at symbol rates up to 1168kHz (for 2.3Mbps operation).The transmit channel consists of a digital-to-analog converter and switched-capacitor pulse forming network followed by a differential line driver. The pulse forming network receives symbol data and generates a standard 2B1Q output waveform. The differential line driver uses a composite output stage combining class B operation (for high efficiency driving large signals) with class AB operation (to minimize crossover distortion).
Features
E1/T1 SINGLE PAIR 2B1Q OPERATION COMPLETE ANALOG INTERFACE 385mW POWER DISSIPATION PROGRAMMABLE POWER 48-LEAD SSOP PACKAGE SCALEABLE DATA RATE OPERATION FROM 2.3Mbps to 160kbps +5V ONLY (5V or 3.3V Digital) -40°C to +85°C OPERATION
Related Datasheets
| Part Number | Description | Category |
| AFE1104 | HDSL/MDSL ANALOG FRONT END | Networking/Communication |
| AFE1230 | AFE1230: G.SHDSL Analog Front-End (Rev. A) | Networking/Communication |
| AFE2124 | Dual HDSL/SDSL Analog Front End | Networking/Communication |
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