One input, one output HDMI/DVI link Enables HDMI 1.3 receive compliant front-panel input Four TMDS channels per link Supports 250 Mbps to 2.25 Gbps data rates Supports 25 MHz to 225 MHz pixel clocks Equalized inputs for operation with long HDMI cables (20 meters at 2.25 Gbps) Pre-emphasized outputs Fully buffered unidirectional inputs/outputs 50 ? on-chip terminations Three auxiliary buffered channels per link Bidirectional buffered DDC bus (SDA and SCL) Bidirectional buffered CEC bus with integrated pull-up resistors (27 k?) Independently powered from +5 V of HDMI input connector DDC bus logic level translation (1.8 V, 3.3 V, 5 V) Input/output capacitance isolation Output disable feature Reduces power dissipation Disables input termination Single-supply operation (3.3 V) Standards compliant: HDMI, DVI, HDCP, CEC 40-lead LFCSP package (6 mm × 6 mm)