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Sampling 16-channel SAR with 8-channel PSoC

Posted: 21 Aug 2014  Print Version  Bookmark and Share

Keywords:Sampling signals  ADC  MCU  SAR  PSoC 4 

Sampling signals by ADC is a regular task for MCU-based applications that requires the conversion of a continuous analogue signal into a series of discrete digital data for MCU processing. In some applications, a single ADC needs to sample multiple channels with a high sample rate. For example, a power monitoring system management sub-system needs to sample the output of regulators to monitor the system working status. In sensor-based applications, the MCU needs to sample multiple sensors to implement system feedback.

One of our customers wanted to sample 16 channels with a 1 MSps SAR using a Cypress PSoC 4. This would result in a total duration of less than 19 us for 16 channels sampling. However, the PSoC4 built-in SARMUX only supports 8 channels. This article describes how we met this design challenge.

Analysing the design requirements
First, we needed to analyse the design requirements carefully. The customer considered a full sampling of 16 inputs as a sampling cycle. As figure 1 shows, the maximum duration of a sampling cycle is limited to 19us. There can be a break among cycles to store SAR results using an interrupt service request (ISR).

Figure 1: Timing for 16-channel sampling.

Figure 2: Design Part I—16 channels SAR sampling. (Click on image to enlarge.)

To achieve this using an 8-channel SAR, we needed to build a customised design based on universal data blocks (UDBs) that are part of the PSoC4 architecture. The idea was to switch channels with a digital signal interconnect (DSI)-based mux, temporarily buffer sampling results in datapath-based FIFOs, and then read them all via an interrupt service routine (ISR).

Datapath is the most valuable portion of a UDB block. Each UDB block contains one datapath and each datapath contains an 8bit ALU with several registers. The details of UDB structure and datapath functions can be found in the PSoC 4 technical reference manual.[2] Each datapath can be constructed as an 8B FIFO. We needed four FIFOs to buffer sixteen 12bit SAR results.

Figure 2 shows a DSI-based switch that can automatically change the current sampled channel among multiple inputs, while figure 3 shows an overview of the hardware FIFOs buffering the sampling results.

Figure 3: Design Part II—four 8B FIFOs to buffer sampling result. (Click on image to enlarge.)

Configuring the SAR
The SAR is configured as single-channel input, single-end mode, 0~Vdd range, and 1 MSps sample rate. It receives a trigger signal to start the channel conversion and an "SDONE" signal is routed to the DSI named "ADC_SDONE". The current SAR component available in the Creator Library does not support output sampling result on the DSI bus. Thus, we needed to import the SAR component into the project and modify it as marked out in red in figure 4.

Figure 4: Design Detail—SAR Component.


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