How to isolate SPI in high bandwidth sensor apps
The bus is conceptually simple, consisting of a clock, two data lines, and a chip select signal. Since data is presented on one phase of the clock and read back on the opposite phase, there is a lot of margin for delays and mismatches in speed. Finally, since the SPI bus is composed of unidirectional lines, it simplifies the implementation in a microprocessor by eliminating flow-control issues. As most traditional isolation devices are unidirectional, the SPI bus lends itself well to isolation using optocouplers or digital isolators.
In industrial applications such as thermal or pressure monitoring systems, communication with the ADC in the sensor front end does not require a high sample rate and hence a high SPI clock rate. Even isolated designs are simple to implement in a wide variety of isolation technologies.
But requirements evolve with time, and the venerable SPI interface has been pushed to its limits by applications with long wire runs, high data rates, and isolation requirements on top of it all. In this article we will look at the SPI bus, its constraints, and how to deal with them in isolated systems.
An application that pushes the limits of isolated SPI performance is high dynamic range sensor interfaces. To create a system with wide dynamic range a designer would start with an analogue to digital converter (ADC) with a good signal-to-noise ratio (SNR), which is usually related to the word length. 16bit words are common, and where higher dynamic range is required, other techniques can be employed such as variable gain amplification of the input and oversampling. Oversampling will trade bandwidth for noise rejection.
If the sample frequency is doubled, typically the noise performance is improved by 3 dB. So, for example, a 75x oversample rate will give an improvement in noise performance and dynamic range of about 18 dB. A 75x oversample of a signal means that an ADC running at 900 ksps would give 18 dB better dynamic range over about a 6kHz band width. The bandwidth and dynamic range can of course be traded off, but in the end, running the ADC as fast as possible has great benefits.
This implies that the SPI bus will have to keep up with this avalanche of data. Let's consider an example with a typical component used for high sample rate applications, such as the ADI AD7985 pulsar ADC, which can run up to 2.5 Msps. We'll see how communicating with it through an SPI bus affects the performance of the signal chain.
The typical ADC handles data in two basic operations (figure 1). First the ADC has a conversion period (tCONV) in which it creates a digital word that represents the voltage at its input. The ADC then transfers this word through a digital interface to a controller during the acquisition time (tACQ). The ADC usually has a minimum cycle time (tCYC) before it can start another conversion, which is approximately the sum of tCONV and tACQ. Sometimes tCYC is shorter, if the ADC has special transfer modes that let acquisition and transfer overlap. For simplicity the following discussion assumes sequential conversion and acquisition.
Figure 1: Simple ADC transfer sequence.
The conversion time and minimum cycle time are the same no matter how the data is transferred. But the acquisition time depends on the properties of the data interface, in most cases the operation of the SPI bus. If the acquisition time is lengthened due to SPI clock rates, the sample rate of the ADC can be severely limited.
SPI clock rate limitations
The SPI link between a microprocessor/FPGA (MCU) and an ADC is illustrated in figure 2. The SPI bus consists of the connections between a pair of shift registers, one in the master MCU and one in the slave ADC. The MCU provides a clock that synchronises the transfer. One edge of the clock shifts data out of the shift registers, and the complimentary edge clocks the data that has been presented into the other end of each shift register in a ring topology. In the case of an ADC there may not be a need to shift data from the MCU to the ADC, so this channel has been eliminated for simplicity, along with the slave select. The ADC fills its internal shift register during the conversion phase of operation, and then shifts the register out during the acquisition phase.
Figure 2: ADC SPI communication block/timing diagram.
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