Samsung preps future SSDs with 3bit V-NAND chips
A 3bit per cell version of the Samsung 128Gbit vertical NAND flash memory will soon hit the market as the Korean tech giant revealed that the chip is only weeks away from shipping. At the same time, Samsung introduced an industry initiative to draw on the capabilities of flash controllers for a variety of storage and compute tasks.
Within a month, Samsung could start shipping solid-state drives using new 128Gbit V-NAND chips with 32 layers and three bits per cell. It promises to deliver twice the capacity at 40 per cent less power than SSDs with planar NAND, said Bob Brennan, head of the company's memory lab in San Jose, speaking in a keynote at the Flash Memory Summit.
Brennan was not able to give performance, power consumption, or endurance details for the new flash design. Samsung announced its first V-NAND products at the event last year, a 24-layer design using two bits per cell. It announced an upgrade to a 32-layer design last month.
Maintaining the same cell-to-cell interference was a top challenge of the latest design, Brennan said. He predicted 256Gbit chips will arrive in 2015 and said the company will eventually get to 100-layer Tbit chips.
"Vertical NAND has now crossed the threshold of cost, and we will continue to scale dollars per GB for years to come," Brennan said.
Samsung's 3D V-NAND flash memory features a vertical architecture stacking 32 cell layers on top of one another, rather than trying to decrease the cells' length and width. Source: Samsung
Separately, Brennan showed preliminary results of how flash controllers could be used to lower latency and improve performance on SSDs. The lab results encouraged the Korean giant to launch an industry initiative to leverage unused capabilities of flash controllers to handle a variety of storage and compute tasks.
A new working group in the Storage Networking Interface Alliance will work on an API for the so-called intelligent storage initiative. The NVMe group that developed a new interface for SSDs riding the PCI Express bus will also start a working group in the area, Brennan said in a brief interview with EE Times after his keynote. The T10 and T13 storage standards groups may also work on the initiative.
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