NV memory: Significance of filament size and shape
A team from Fudan University and the Semiconductor Manufacturing International Corp., Shanghai, , used a 128k-bit ReRAM memory array of bi-layer AlOx/WOx memory cells to evaluate all the possible (4) different combinations of set and reset pulse trains that either increased or decreased in amplitude and then introduced a new one. This new pulse sequence is called FS-DSUR (fast speed-down set up reset), where the pulses are merged together in a single stepped pulse. Removing the read verify between pulses saves both time and power. The resistance of the growing filament is monitored continually during set pulse steps, and the pulse, or pulse train, is terminated when the required resistance value is reached.
Figure 1: Set pulses reducing in amplitude create a parallel shaped filament, while a set pulse train increasing in amplitude creates a frustum conical shaped filament with the broadest part of the section in contact with the bottom electrode.
The interpretation is that set pulses reducing in amplitude create a parallel shaped filament, while a set pulse train increasing in amplitude creates a frustum conical shaped filament with the broadest part of the section in contact with the bottom electrode (figure 1).
The filament options not shown in figure 1 are the incomplete cylindrical filament and the over SET conical filament; the latter can occur with both SET-up and SET-down type pulses.
One of the advantages of the step-down pulse (where a cylindrical filament is formed) is that a reset pulse of a given amplitude will create a wider gap in the filament and therefore a higher off-state resistance. This latest work reported that both versions of DSUR, steps and discrete pulses, were able to provide write/erase (W/E) endurance of 109 cycles with the new FS-DSUR marginally better. In all cases, a step-down reset offered no advantage. This work also discovered that there was a maximum in the individual step width, or pulse width, of 60nsecs in order to obtain the unverified 109 W/E cycle endurance.
IMEC, Belgium was well represented at VLSI 2014. One paper  used a TiN/Ta2O5/Ta memory structure and explored the relationship between the thickness of the tantalum (acting as a scavenger layer for oxygen when the device is formed) and its data retention properties.
Figure 2: A model explaining retention changes for both the reset and set state.
A model to explain retention changes for both the reset and set state was developed (figure 2). It leads to the conclusion that retention is strongly related to the thickness of the upper electrode and its scavenging ability, rather than it is to the properties of the filament alone.
A thick upper Ta electrode of 30nm Ta/6nm Ta2O5 compromises the elevated temperature data retention in the high-resistance state (HRS), and not the LRS, while a thin upper electrode 10nm Ta/6nm Ta2O5 has the opposite effect.
In the LRS for a thick upper electrode there are two directions in which oxygen ions can move (small red arrows) while for a thin electrode there is only one (figure 2). The result is a large change in resistance (data retention) for the LRS with thin electrodes when subjected to thermal stress. For the thick upper electrode, it is the HRS state it is most effected by thermal stressing because there is a higher density of oxygen vacancies close the lower electrode that can move towards the higher resistance region of the filament and reduce its resistance.
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