FPGAs afford server boosts in datacentres
Microsoft Corp. reported a 95 per cent ranking server throughput improvement in a paper describing a medium-scale deployment of a Stratix-based reconfigurable fabric, dubbed Catapult, on a system consisting 1,632 servers to speed up processing of massive volumes of data.
Altera already announced that it has been working with Microsoft Research to leverage its FPGAs in order to accelerate portions of the Bing search engine (see Altera forms broadband, data centre partnerships).
"We set a performance target that would be a significant throughput gain, while simultaneously permitting more advanced search ranking models to be run. Compared to a pure software implementation, our reconfigurable acceleration fabric permitted a 90 per cent improvement in throughput at each ranking server, with great system stability," said Doug Burger, director of Client and Cloud Applications in Microsoft Research's Technology division, in a press release.
Catapult enhanced the ranking throughput of each server by a factor of 95 per cent for a fixed latency division under high load, according to Microsoft. When maintaining equivalent throughput, the fabric reduced the tail latency by 29 per cent.
Based on the results, Bing plans to roll out FPGA-accelerated servers to process customer searches in one of its data centres starting in early 2015.
(a) A block diagram of the FPGA board. (b) A picture of the manufactured board. (c) A diagram of the 1 U, half-width server that hosts the FPGA board. The air flows from the left to the right, leaving the FPGA in the exhaust of both CPUs. Source: Microsoft
Microsoft is relying heavily on Intel's Xeon processor packs for its servers. And it is interesting to note that during the same week at the Gigaom Structure'14 conference, Diane Bryant, Intel's data centre division lead engineer, presented the future of Xeon processors with integrated FPGAs in a single package, socket compatible to the company's standard Xeon E5 processors.
"The FPGA provides our customers a programmable, high performance coherent acceleration capability to turbo-charge their critical algorithms. And with down-the-wire re-programmability, the algorithms can be changed as new workloads emerge and compute demands fluctuate", Bryant explained. Intel expects this new hardware combination could deliver over 20X performance gains compared to more traditional ASIC-based solutions.
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