Adaptive voltage scaling boosts energy efficiency
A common way of minimising silicon chip power consumption is to change frequency and supply voltage based on the need for computing power over time. A lower supply voltage is highly effective in reducing power and energy consumption as power dissipation is proportional to the square of the supply voltage. If the demand for computing power is low, the clock frequency of the microprocessor can be decreased; and when the clock frequency is lower, the supply voltage can also be lower. This technique is called dynamic voltage scaling (DVS) and is commonly implemented by an open-loop approach where pre-determined combinations of frequency and supply voltage are stored in a look-up table.
DVS offers much better efficiency compared to fixed voltage supply and facilitates a great deal of energy saving, but does not fully utilise the potential of voltage scaling. Shortcomings of DVS include the necessary voltage margins to guarantee safe operation taking into account the static and dynamic regulation window of the power supply, and also the silicon process variations and operation within different environmental conditions.
Adaptive voltage scaling
Adaptive voltage scaling (AVS) deals with the shortcomings of DVS via a closed-loop real-time approach that adapts the supply voltage exactly to the minimum required voltage for the actual clock frequency and workload demand of the individual processor chip. It also automatically adjusts to compensate for process and temperature variations in the processor.
Modern high-performance microprocessors change workload and operating conditions within nanoseconds therefore real-time regulation of the microprocessor supply voltage puts a high demand on control-loop bandwidth and requires close monitoring of computing hardware performance in the feedback loop. This is now possible with the recent release of AVS controllers that include dedicated IP and hardware.
Typical differences in energy consumption between fixed supply voltage, DVS and AVS are shown in figure 1. Note that lowering the frequency alone does not affect the energy consumption. The average power will decrease but lower clock frequency means that a specific computing task takes longer time, e.g. if the frequency is lowered to f/2 the computing time will be twice as long. The supply voltage must be decreased to realise energy savings.
Figure 1: Comparison of energy savings in a microprocessor with fixed supply voltage, DVS and AVS.
The feedback loop includes the board mounted power supply (BMPS) and is based on monitoring the computing performance of the processor chip, effectively eliminating any excess voltage margin associated with DVS. Because it actually senses the voltage directly on the chip, the loop also provides the ultimate remote sense connection for the voltage regulator feedback. This also has the effect of eliminating any voltage error due to voltage differences in the ground plane between the BMPS and the microprocessor.
|Related Articles||Editor's Choice|