Semtech reveals HMC-compliant PHY IP
Semtech Corp. has successfully completed the electrical compliance testing of its Snowbush 28nm Platform Physical Layer IP, in support of the Hybrid Memory Cube (HMC) specification for ultra-fast, next-generation memory.
The Snowbush Platform IP has met the interoperability requirements of the HMC standard with significant margin and passed the rigorous testing required by Micron, a founding developer of the Hybrid Memory Cube Consortium. This ensures compliance and enables system designers to deploy I/O designs that support the HMC standard on their ASICs and SoCs.
Semtech worked closely with Micron to perform silicon measurements on actual hardware to ensure that all the critical elements of this high-speed memory interface meet the requirements of the HMC specification. Such testing relieves ASIC or SOC developers from conducting their own pre-silicon validation and encourages the early use of the interface on systems-level chips.
Micron supplies the HMC memory chips and Semtech will provide the Snowbush Platform IP to companies that will integrate it into their system-level chips to implement the high-speed link to the memory chip.
HMC has been recognised by the industry as the long-awaited answer to addressing the limitations of efficiency and power consumption imposed by conventional memory technology. With the ability to deliver up to 15 times the bandwidth of a DDR3 module, with 70 per cent less energy and 90 per cent less space than existing technologies, HMC's abstracted memory enables designers to devote more time to HMC's ground-breaking features and performance and spend less time navigating the multitude of memory parameters required to implement basic functions. In addition, HMC manages error correction, resiliency, refresh and other parameters exacerbated by memory process variation.
The Snowbush IP supporting HMC in 28nm is available. Pricing depends on configuration and the number of instantiations in a design.
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