Phase change memory: Multi-level to multi-tasking
Of particular interest are the two PCM papers from the joint Macronix International and IBM T.J. Watson Research Centre project. The first paper (11.1) is titled "A Double-Density Dual-Mode Phase Change Memory Using a Novel Background Storage Scheme," and it offers a new approach to multi-level cell (MLC) PCM.
In the past IBM, Zurich, has offered a solution to the drift problem that limits the use of PCM in an MLC mode. This new approach to multi-level is different because it allows each PCM cell to operate concurrently in two modes: foreground and background. More importantly, each cell has a bit capacity that is the product of the number of bits in the foreground and background modes. In the VLSI 2014 paper, a 4bit per cell will be presented, the equivalent of 16 levels. It is conceivable that such a memory could operate in a multi-tasking role serving two separate applications.
The authors describe the way they achieve the multiple states as "stressing the memory cell with current that can shift the threshold for reset switching." It would appear that the two normal high and low resistance states associated with a single-bit PCM cell can be further modulated. However, what is remarkable is a method has been found where the background state of the R-I characteristics is remembered when the device is switched between its more conventional high and low resistance foreground states.
Figure 1: The speculative I-V characteristics of a PCM operating as a 3bit per cell in foreground and background mode.
While we wait for the publication of the paper, and the detail of the way in which the "stress" is applied, one can speculate how such a dual-role operation might possibly be achieved and some of the problems that would need to be overcome. In figure 1, for the purposes of discussion I have illustrated the speculative I-V characteristics of a PCM operating as a 3bit per cell in foreground and background mode. The red and green data levels are foreground data while the black dots and associated I-V curves are the background.
Ideally, it would be desirable to find a pulse sequence that can be applied to the cell without a pre-read and latch requirement. It might be the "stress" that the authors describe is a way of causing the memory to always retain some structure-based knowledge of its initial foreground data state.
A suggested way in which such a device might operate for writing foreground data is as follows. Start with a cell in its 1(01) that is to be written to its 0(01)state, i.e., a change of foreground data from 1 to 0. Apply a "stress" pulse followed by a series of four pulses that are each sufficient in reset current amplitude to reset the device from each of its foreground states. Once the device has reset, the remainder of the pulses in the sequence are incapable (insufficient voltage) of having any further effect, so they will be ignored. In the example, 1(01)-to-0(01), the second pulse in the sequence will reach the reset threshold and effect the reset. In each case, the amplitude of the reset pulse is only sufficient to reset the cell to a resistance and threshold voltage value proportionally related to its position in the sequence. The pre-stress pulse conditions the cell so single pulse reset discrimination is possible.
What if the device is in the high resistance (0 data) foreground state? In that case, a similar write "1" pulse sequence will be applied. Each pulse will be of increasing voltage amplitude but only sourced with sufficient current to set the device. If the write 1 pulse sequence is applied to a device already in the logic 1, then a pre-read would be one solution that would avoid over-writing problems.
For writing background data, the problem is a little more difficult and will most likely need to involve a two-step process. Figure 2 is a suggested means of writing background data. Initially pre-read, if the foreground is in the 1 state; then apply the reset sequence, which will carry the background data to the 0 foreground (blue line) state; then apply a single set pulse (orange line) to achieve the desired set background state. The upper curves of figure 2 (a) and 2(b) are for transitions 1(00) to 1(11) and 1(11) to 1(00) respectively.
Figure 2: A suggested means of writing background data.
For transition within the 0 state, apply the pulse sequence this time with a current source that will write the desired set state. Then apply the reset pulse sequence. Figure 2 (c) and (d) illustrate the background data transitions of 0(00) to 0(11) and 0(11) to 0(00) respectively.
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