Accellera updates Verilog-AMS with verification, modelling
The Verilog-AMS 2.4 includes extensions to benefit verification, behavioural modelling and compact modelling. There are also several clarifications and over 20 errata fixes that improve the overall quality of the standard.
"Verilog-AMS 2.4 is the result of the hard work and collaborative effort of the Verilog AMS Working Group (WG) who came together to deliver this standard," said Scott Little, chair of the Verilog AMS WG. "This revision adds several features that users have been requesting for some time, such as supply sensitive connect modules, an analogue event type to enable efficient electrical-to-real conversion and current checker modules."
Verilog-AMS is a mature standard originally released in 2000. It is built on top of the Verilog subset of the IEEE 1800-2012 "SystemVerilog—Unified Hardware Design, Specification and Verification Language." The standard defines how analogue behaviour interacts with event-based functionality, providing a bridge between the analogue and digital worlds. To model continuous-time behaviour, Verilog-AMS is defined to be applicable to both electrical and non-electrical system descriptions. It supports conservative and signal-flow descriptions and can also be used to describe discrete (digital) systems and the resulting mixed-signal interactions.
The Verilog-AMS WG is currently exploring options to align Verilog-AMS with SystemVerilog in the form of a dot standard to IEEE 1800. In addition, work is underway to focus on new features and enhancements requested by the community to improve mixed-signal design and verification.
The revised language reference manual is available for download from the company's website.