DSP processors notch up low power consumption
Synopsys has released a series of 32bit processors designed for low-power embedded digital signal processing (DSP) applications.
The ARC EM series comes with an optional floating point unit (FPU), and are based on the ARCv2DSP instruction set architecture featuring over 100 additional DSP instructions to accelerate signal processing algorithms, including vector and complex MUL/MAC operations.
The processor cores integrate a unified, single-cycle 32x32 MUL/MAC unit with 40bit/72bit accumulators. Other features include fractional support with saturating arithmetic, rounding and non-rounding instructions, and vector support.
Characteristic of the ARC series, the processors are configurable, enabling optimum balance of DSP and RISC performance as well as power and area efficiency. This also allows memory and SoC peripherals to be directly connected to the processor for single-cycle access, helping minimise system-level latencies and silicon area.
Figure 1: The ARC EM5D supports up to 2MB instruction and data closely coupled memory (CCM), while the EM7D features up to 32KB of instruction and data cache. Both deliver excellent performance efficiency, consuming as little as 7µW/MHz in a typical 40nm LP process technology.
The DesignWare ARC MetaWare development toolkit is designed for debugging and optimising embedded software targeted for ARC processors, including the new EM DSP release. It includes an enhanced C/C++ compiler supporting the new DSP instructions for efficient algorithm development. The toolkit also includes a DSP software library of fixed-point math functions and an instruction-accurate simulator that includes accurate modelling of the new DSP operations.
ARC EM5D and EM7D processors are scheduled for general availability in July.
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