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Address SoC routing congestion with 2.5D SiP

Posted: 05 Jun 2014  Print Version  Bookmark and Share

Keywords:embedded systems  System on Chip  SoC  System in Package  SiP 

Not very long ago, embedded systems were made up of logic spread across multiple chips—for example, the CPU sub-system. Memory, the analogue components, and so on, were each on their own IC. The advantage was that each chip could be independently designed at its appropriate process technology node (90nm, 130nm, etc.). However, the inter-connection between the chips consumed a significant amount of power, and there was high inter-chip communication latency as well as even higher risk of failure.

Then came the era of the System on Chip (SoC) where the various components (digital logic, analogue logic, and memory sub-system) were placed on the same silicon chip. Thus the increased power consumption and latency issues observed with inter-chip communication in the previous design mechanism was ruled out. However, the disadvantage was that as the components were integrated in the same silicon, they had to be built at the same technology node (65nm, 40nm, 28nm, and so on).

While some logic, particularly the main processor, adds a greater value if it is designed at the latest technology node, the other components, such as memory, might not add that much value. However, the dilemma is that using traditional System-on-Chip methods, the chip designer has to choose the same process technology for all the logic. In addition to forcing the designer to create a less than silicon-efficient design, this also hindered reusability of some blocks, such as the CPU sub-system, as independent verified logic in the next system design.

The best of both worlds approach that the electronics industry has come up with to solve this dilemma is the System in Package (SiP) in a 2D package. Here multiple chips (DIE) are placed on a common substrate. Thus there can be a CPU-sub-system on one die, a memory sub-system on another, and analogue logic on a third die (figure 1).

Each DIE can be designed at its appropriate process technology node and later reused in later designs as Known Good DIEs (KDGs) which have been tested at wafer level. This reduces the time to market for the complete system, as KGDs can be reused with newer dies. The substrate carries a low power, low latency, high speed communication link between the DIEs.

Figure 1: 2D package.

The DIEs are mounted on the SiP substrate by flip-chip bumps. The copper tracks on the substrate are many times wider than that on the DIEs. However, this creates a problem of placement, as it limits the number of dies that can be accommodated on the substrate because of routing congestion, which ultimately impacts performance and power consumption.

Relieving routing congestion with 2.5D SIP
The solution to this problem is 2.5D packaging, where a silicon interposer is added between the DIEs and the substrate. The interposer is a low power, low latency, high speed communication link between the chips. The DIEs are mounted on the interposer using micro bumps that are many times smaller than the flip-chip bumps connecting the interposer to the substrate.

The copper tracks on the upper layer of interposer are almost of the same dimensions as those on the DIEs. The interposer has TSV (Through Silicon Vias – copper connections) connecting the tracks on the upper layer to those on the lower layer. It allows thousands of connections between the dies. Thus, by using the interposer the routing/congestion problems faced in 2D design are overcome.

Figure 2: 2.5D package.


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