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Identify electrically overstressed LEDs (Part 3)

Posted: 02 Jun 2014  Print Version  Bookmark and Share

Keywords:LEDs  electrical overstress  EOS  Structure 2  Structure 3 

Read Part 1 here and Part 2 here.

The LEDs tested demonstrated a wide range of EOS threshold failure levels depending on the LED chip structure, number of LED chips and device package construction. In general, single-chip high-power LEDs with multiple contact vias are most robust against EOS events. Low-power plastic packages are more susceptible to damage from EOS events. EOS susceptibility of multi-chip COB LEDs varies based on package construction; however, for all the tested parts, as the power-to-failure increases, the time-to-failure decreases.

Failure mechanisms
After determining EOS robustness of the LEDs, we conducted failure analysis to analyse the relationship between failure modes and overstress conditions. This analysis helps to identify an EOS failure and estimate the dimensions of the electrical transient that caused the failure.

The failure analysis procedures consisted of electrical characterisation, optical inspection and chemical deprocessing. We manually tested electrical characteristics such as junction leakage current and breakdown voltage. We dissolved the silicone encapsulant material of the damaged LEDs in a chemical solution to expose the LED chip surface and inspected the damage under a microscope at high magnifications (100X and greater).

The fundamental cause of EOS failure is localized Joule heating of the materials in the LED along a current or power-dissipating path. The highest current density in an LED typically occurs near the metal bond pad and current-spreading metal line, or near contact vias. Therefore, EOS failures often exhibit certain welldefined features. For a device with bond wires and metal lines for current spreading, fused bond wires and damage near the metal line or bond pad are typical EOS characteristics. For a device with multiple contact vias, damage near the vias is typical.

We observed three major failure modes in our tests:
1. A failure induced by low energy, long duration stress.
2. A failure induced by intermediate energy, intermediate duration stress.
3. A failure mode induced by high energy, short duration stress.

LEDs show an inverse relationship between power- and time-to-failure. As pulse power increases, time-to-failure decreases, and as pulse power decreases, time-to-failure increases. This means that LEDs can operate on larger amounts of power for a shorter time and smaller amounts of power for a longer time.

We focused our failure analysis on Structure 1 and Structure 3 devices. The failure mechanisms for the Structure 1 and Structure 3 LEDs followed a similar pattern, shown in figure 6 and figure 7. In each case, the pattern is divided into three time regions, as follows:
Region 1: Time-to-failure greater than 5 ms.
Region 2: Time-to-failure from 0.5 ms to 5 ms.
Region 3: Time-to-failure less than 0.5 ms.

Figure 6: Pulse-power-to-failure vs time-to-failure for Structure 1 LEDs.

Figure 7: Pulse-power-to-failure vs time-to-failure for Structure 3 LEDs.


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