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7nm, 5nm scaling compels adoption of new materials

Posted: 26 May 2014  Print Version  Bookmark and Share

Keywords:transistors  10nm  semiconductor  FinFET  SOI 

Shrinking down transistors from 10nm to 7nm and below calls for deciding on semiconductor materials for substrates, channels, gates, and contacts among the available variety.

"For logic [at 14nm and 10nm], the architectures are defined," said Raj Jammy, general manager of the semiconductor group at Intermolecular Inc. and one of several scheduled presenters on the topic at Semicon West in July. "In most cases, they are FinFETs, but there is also an alternate option, which is fully-depleted SOI."

For both 10nm and 7nm, he thinks that high-k metal gates will tend to be dominant, but the real challenge will be the channel itself. At 10nm, germanium (Ge) will likely be one of the channel materials. "But the moment you add Ge, a whole range of questions open up."

Within the 300mm development line at the State University of New York College of Nanoscale Science and Engineering, several alternate device architectures are already under development. "Silicon nanowire devices have been developed on 300mm wafers and evaluated for radiation hardened applications," said Christopher Borst, associate professor of nanoengineering at SUNY CNSE and another scheduled Semicon West speaker.

5nm material adoption

Researchers expect semiconductors will adopt many new materials as they advance from the 16nm-11nm node (left) to the 5nm node (right).

In parallel with the silicon nanowire effort, SUNY CNSE researchers have a development focus on materials beyond Si and are working with industrial and research partners.

"III-V layers are being evaluated as channel materials for next-generation devices," said Borst. "We are committed to developing modules for III-V gate stack, contact, and source-drain engineering that are compliant with environmental guidelines, while driving to sub-10nm device performance targets."


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