Clock translator provides jitter cleanup, synchronisation
The AD9554 generates an output clock synchronised to up to four external input references. The digital PLL (DPLL) allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry continuously generates a low jitter output clock even when all reference inputs have failed. It has adaptive clocking capability that allows the user to dynamically change the DPLL divide ratios while they are locked.
The device operates over an industrial temperature range of ?40°C to 85°C. It dissipates only 940mW of power while generating up to eight output clocks over an output range of 430kHz to 941MHz, synchronised to four 2kHz to 1GHz external input references, with a loop bandwidth as low as 0.1Hz.
The clock's integration, adaptive clocking capability, and OTN mapping algorithm embedded in DPLL, can reduce system costs by simplifying clocking circuitry and eliminating software control routines. Output jitter is 250fs over the 50kHz to 80MHz range and 350fs over the 12kHz to 20MHz range.
The device is housed in 72-lead LFCSP package, and is available at $21.33/1k.
The device has an adaptive clocking feature, which allows dynamic adjustment of feedback dividers in OTN mapping/demapping.
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