Divide by N to synchronise DC/DC converter clocks
First application: Single DC/DC plus PMIC
In the first automotive application, figure 1, the PMIC outputs its own self-generated switching frequency clock of 2.2MHz (above the MW band) and this is to be divided down to clock the TPS54360-Q1 at a frequency below the MW Band. Dividing by four gives 550kHz, which is within the MW band. Dividing by eight (the next power of two) would give a low switching frequency of 275kHz. Dividing by five gives a frequency of 440kHz, just below the MW band. The goal is to use as high a switching frequency as possible to minimize passives' sizes (the inductor's size is inversely proportional to switching frequency), whilst placing the fundamental below the MW Band. Dividing a clock by non-powers of two requires a bit more thought. In this particular application the solution needs to be low cost, robust and the ICs automotive-qualified. There is no requirement for the clock to have a 1:1 mark-to-space ratio, which simplifies the solution.
Figure 1: Two DC/DC Converters with Clock Synchronisation at Different Frequencies via a Divide by Five. TPS54360-Q1 is switching below the MW band and the PMIC above it.
The clock divider
Using a decade counter like CD74HC4017 and feeding back one of its outputs to the reset pin might seem one way to do it, but this will mean that the reset is an undesirable narrow (or "runt") pulse that lasts only as long as it takes for the flip-flop producing it to reset its own output. The better solution shown in figure 2 is to use a shift register SN74AHC595 and a logic inverter SN74AHC1G04, which are both also available as automotive-qualified ICs, SN74AHC595-Q1 and SN74AHC1G04-Q1. For High Reliability applications, an SN74LV595A-EP and inverter SN74LVC1G14-EP can be used instead. For space-rated applications, the slower SN54HC595-SP and inverter SN54HC04-SP (or other) can be used. Examining the datasheet shows that each of the shift register's outputs is double-buffered, in the sense that two flip-flops are cascaded per output. The reset that is generated by the output of the second of the flip-flops in the double-buffer is only resetting the first flip-flop in it and therefore it lasts one full clock cycle.
Figure 2: A Divide by Five Clock Circuit, Showing its Four Outputs. The 10k pull-down is for when OE/ is high.
Figure 3: Divide by Five Waveforms. The rising edges mark the 0, 20, 40 and 60% phases that can be used to synchronize the converters.
The waveforms are shown in figure 3 and show that a divide by five clock output is available in four places, each with a different mark-to-space ratio and having different phases. The term "phases" here refers to the rising edges of the outputs, which occur at different points in time and are used to synchronize the DC/DC converters. The term "mark-to-space ratio" is the ratio of the time the signal is high divided by the time it is low. You can opt to use whichever output is most useful for your application. In this application, the TPS54360-Q1 RT/CLK input is falling-edge triggered and any of the Q outputs can be used, once they have been inverted. Note that in applications where the input voltage is doubled such as is the case for a lorry running off a 24V battery or other 24V industrial applications, then a divide by six could have been constructed using the solution in figure 3, but moving the reset from QC to QD. (When the input voltage to the DC/DC converter is doubled and if the switching frequency remains the same, then the on-time is halved. Dividing by six reduces the switching frequency and increases the on-time to keep it above the minimum on-time of the IC.)
Figure 4: Cascaded SN74AHC595 for a Larger Divide by N Ratio e.g. N=17.
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