FPGA breaks high-density, power-hungry barrier
Lattice Semiconductor has launched its ECP5 FPGAs targeted at providing low cost connectivity to ASICs and ASSPs with improved routing architecture, dual channel SERDES, and enhanced DSP blocks for up to 4x improved multiplier utilisation.
These days, the majority of FPGA vendors aim at replacing ASICs and ASSPs in systems. Lattice takes a different view. For the price-conscious, high-volume markets it is targeting—things like small cells, microservers, broadband access, and video applications—Lattice intends its ECP5 FPGAs to act as companion chips. The idea is that the stable functions will be implemented in an ASIC or ASSP, while new and evolving features and functions will be implemented in an ECP5.
The IC comes in various options offering from 25K to 85K look-up tables (LUTs) at a cost 40 per cent lower than alternatives according to the manufacturer, while delivering twice the functional density of competing solutions.
"Most of our competitors focus on making larger devices with complex routing, then try to scale the FPGAs back to offer smaller devices, but their architecture does not scale back very well" explains Bruce Fienberg, Director of Corporate Communications at Lattice Semiconductors.
"Because we focus on devices below 100K LUTs, we are able to simplify routing for a more efficient use of silicon, hence the higher density of our 40nm designs versus our competitors' devices built in 28nm" he added.
The devices are specifically designed to closely match a number of applications, with improvements on the DSP block and support for very low cost and low power SERDES links. The ECP5 FPGAs provide the flexible connectivity required in outdoor small-cells, at extremely low-cost. They can also enable a smart SFP (small form-factor pluggable) transceiver solution for broadband access equipment, including integrated operation and maintenance.
Outside of communications, ECP5 devices offer low cost, low power PCI Express side-band connectivity for microservers. For industrial video cameras, ECP5 FPGAs can implement the entire image processing functionality in a device that consumes under 2W. Enhancements leading to 30 per cent lower total power than other FPGA solutions include stand-by mode operation of the individual blocks including SERDES, dynamic IO bank controllers and reduced operating voltage.
This enables single channel 3.25Gb/s SERDES functions starting below 0.25W, and quad channel SERDES functions starting below 0.5W for supporting a broad range of interface standards, including DDR3, LPDDR3, XGMII and 7:1 LVDS, PCI Express, Ethernet (XAUI, GbE, SGMII) and CPRI.
The ECP5 FPGA Family is supported in version 3.0 of the Lattice Diamond software tool, available now.
(With inputs from Clive Maxfield)
- Julien Happich
EE Times Europe
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