Initialising MPC5777M clock generation module
One difference between the MPC5777M and the MPC5746M is the clock architecture. The MPC5777M supports a main computational core clock of 300MHz whereas the MPC5746M supports a main computational core clock of 200MHz.
While the MPC5746M supports a 1:1 ratio between Core clock (200MHz) and Crossbar (200MHz), the MPC5777M supports a 3:2 ratio between Core clock (300MHz) and Crossbar (200MHz).
This document details the MPC5777M specific PLL and clock divider settings to achieve 300MHz Core 0 / Core 1 and 200MHz Fast Crossbar (FXBAR) / Core 2 operation. In addition, the document describes the Progressive Clock Switching feature, which supports a smooth ramp-up and ramp-down of device system clocks, for a 300MHz clock example. The calculations for this example can be used for a 200MHz source clock application by simply changing the inputs to the formulas.
View the PDF document for more information.
Originally published by Freescale Semiconductor at www.freescale.com as "Initializing the MPC5777M Clock Generation Module and Progressive Clock Switching Feature".