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On-chip interconnect costs head for further study

Posted: 28 Mar 2014  Print Version  Bookmark and Share

Keywords:interconnect  BEOL  Qualcomm  Globalfoundries 

As a result of 16nm chips moving to production in 2014, companies are actively developing the 10nm and 7nm technology nodes. These generations are interconnect heavy, more than 50 per cent of their cost is due to the back-end-of-line (BEOL) wiring levels, and designs are dominated by interconnect delay.

"Interconnect performance/area/cost scaling the foremost issue for 10nm and 7nm nodes," Geoffrey Yeap, VP of technology at Qualcomm, said in a keynote at the 2013 International Electron Devices Meeting.

BEOL cost

First, interconnect performance and reliability depends heavily on diffusion barriers, liners and cap layers for copper. These can be improved in multiple ways.

For example, engineers can make these structures thinner and improve their quality by using CVD or ALD instead of PVD and by using alternative materials. At the May conference, researchers from IBM and Applied Materials will present results of their work on multi-layer SiN caps and cobalt caps and liners that provide a 1000x improvement in electromigration lifetime, as well as enhancements in time-dependent dielectric breakdown.

Interconnect delay

Separately, double patterning techniques have become common in the BEOL. For further scaling, setups like self-aligned double and quad patterning and triple lithography/etch with block masks are necessary. Companies are innovating to lower the processing costs for these technologies while meeting overlay, line edge roughness, uniformity, variability and layout requirements.

Another emerging trend is the integration of memory devices into logic BEOLs. This includes stacked capacitors for embedded DRAM as well as resistive RAM for MCUs, both of which have seen product announcements recently. At the May conference, Intel will present a system to integrate 3D capacitors into 22nm copper/low-k stacks. The capacitors provide an eDRAM density of 17.5Mb/mm2, which Intel claims is 3x higher than the most aggressive SRAM.

The dramatic increase of copper resistivity at smaller nodes is motivating research on alternative conductors. Researchers from AIST will show 8nm graphene interconnects that demonstrate an important milestone: lower resistivity compared to copper.

In addition, Imec will show vertical carbon nanotube interconnect prototypes with a mean free path comparable to copper. These promising proof-of-concept demonstrations are expected to motivate the process integration research required to take these technologies to the next level. Besides carbon-based interconnects, several other materials are being studied.

Meanwhile, 3D interconnect systems are being actively pursued by the DRAM industry for wide I/O DRAM and hybrid memory cubes. At the conference, CEA-LETI will present experimental results on monolithic 3D technology, which provides through silicon vias (TSVs) as small as 50nm. The high density of TSVs will provide a 55 per cent area reduction and a 47 per cent energy-delay product improvement for a 14nm FPGA. In addition, Globalfoundries will describe a near-zero keepout zone around TSVs.

In addition to these topics, innovations are occurring in ultra-low-k dielectrics, circuit techniques to handle interconnect issues, short-wire architectures, and many other areas. The next few years should be exciting for interconnect technologists.

- Deepak Sekar
  EE Times





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