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Chip design tool delivers tenfold performance boost

Posted: 25 Mar 2014  Print Version  Bookmark and Share

Keywords:place-and-route  IC  Synopsys 

Synopsys recently upgraded its place-and-route chip design software, and its beta customers are already raving about the IC Compiler II's performance boost reaching up to 10 times by utilising just one-fifth of the memory of its predecessor.

The update leverages new algorithms and the multi-threading capabilities of modern processors for many of its performance gains. Available in mid-June, the IC Compiler II employs a new design database. That's expected to stretch users' transition to the new code over several years.

Six customers, including LSI Logic, Panasonic and Samsung, issued statements support for the new product. "We observed a boost to the throughput of our design exploration flow by at least 10 times," Mark Dunn, an EVP of SoC engineering at Imagination Technologies, told us. His company used the software to define a floor plan for a PowerVR Wizard GPU core.

STMicroelectronics also reported creating a floor plan 10 times faster. An EDA manager there said it created a design implementation five times faster than those on previous products while handling partitions two to three times larger than previously possible.

An EDA manager at Renesas reported "at least seven times runtime and three times memory improvement."

Mike Demler, a senior analyst at Linley Group, called the product a significant clean-up of blended new and legacy code from Synopsys and companies it acquired over the years, including Avanti and Magma Design. The original product was the company's biggest revenue generator—a position it will likely continue to hold, since licensees will need to purchase the upgrade as a new product.

The biggest trade-off with the upgrade is the lack of interoperability between it and the previous generation, he said. The IC Compiler-II "creates another proprietary database to succeed Milky Way."

Demler expects Synopsys to need to support both versions of the tool for some time. However, he anticipates that Synopsys eventually will discontinue both the original IC Compiler and separate place-and-route software acquired with Magma.

Both Demler and Gary Smith, a veteran EDA analyst, expect Synopsys to remain in the lead among the top three companies in the sector, followed by Cadence and Mentor Graphics.

Smith said Cadence and Mentor are doing a good job moving into the new territory of electronic system level (ESL) design tools. However, he also said recent acquisitions at Synopsys seem less focused. "They are floundering a little bit trying to figure out what to do next. I don't see them target ESL as much as I'd like to see because it's where the whole sector is going."





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