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28nm node at the final frontier of Moore's Law

Posted: 20 Mar 2014  Print Version  Bookmark and Share

Keywords:FD-SOI  Moore's Law 28nm  SoC 

MonolithIC 3D President and CEO Zvi Or-Bach believes that for most SoCs, 28nm will be the standard node supporting minimum component costs in the years ahead. He reiterates that the electronics industry is facing a paradigm shift because dimensional scaling is no longer the ideal path for cost scaling.

We have been hearing about the imminent demise of Moore's Law quite a lot recently. Most of these predictions have been targeting the 7nm node and 2020 as the end-point. But we need to recognise that, in fact, 28nm is actually the last node of Moore's Law.

Beyond this point, we can continue to make smaller transistors and pack more of them into the same size die, but we cannot continue to reduce the cost. In most cases, in fact, the same SoC will actually have a higher cost!

The famous Moore's Law was presented as an observation by Moore in his 1965 Electronics paper "The future of integrated electronics," in which he said:

FD-SOI

Click on chart for in-depth coverage of why ST sees FD-SOI as flag bearer for Moore's Law.

"The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years."

Clearly, Moore's Law is about "The complexity for minimum component costs," and the minimum component cost will be at the 28nm node for many years.

The chart on the right was presented by ST's Joël Hartmann (EVP of Manufacturing and Process R&D, Embedded Processing Solutions) during Semi's recent ISS 2014 Europe Symposium.

Hartmann is making the case that the "Moore's Law discontinuation due to cost stagnation or increase" applies to bulk technologies, which is the technology base of the majority of the industry. ST's information is backed by GlobalFoundries' claim that the lowest-cost transistor is at the polySiON 28nm node. Beyond 28nm, scaling becomes extremely expensive due to double litho, HKMG and FinFET. The increase in wafer cost eats away the 2X transistor density gain per node.


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