CEA-Leti reduces memory gate to 16nm via poly-Si spacer
Split-gate flash memory is composed of one access transistor and another memory transistor that contain a charge-trapping layer such as nitride or Si nanocrystals among others.
The research centre explains that the memory's architecture uses low-access voltage and minimises drain current during programming, contributing to a decrease of the programming power compared to one-transistor NOR memories.
In split-gate memories, programming energy and memory gate length are directly correlated so that when the former is decreased, the latter is also decreased.
CEA-Leti reduced the memory's gate down to 16nm using a poly-Si spacer formed on the sidewall of the select transistor. This approach avoids costly lithography steps during fabrication and solves misalignment issues, which are responsible for a strong variation of the electrical performances, such as the memory window.
TEM images of ultra-scaled self-aligned split-gate device, with a memory gate length of 16nm.
The main challenges of this self-aligned technology concern the precise control of the spacer memory gate shape and of the memory gate length.
Spacer gate has to fulfil two difficult requirements: being as flat as possible in order to get a silicidation surface as large as possible while insuring a functional contact, and getting a steep edge in order to control the drain-junction doping.
- Julien Happich
EE Times Europe
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