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Silicon Basis lowers SRAM power via standard logic

Posted: 07 Mar 2014     Print Version  Bookmark and Share

Keywords:SRAM  logic  Silicon Basis 

Silicon Basis has developed a system of building SRAM on a standard logic process, cutting the power consumption in half and decreasing the voltage below that of the foundry memories.

The system allows the memories to source power from the logic's voltage source thus eliminating the need for a second DC-DC converter. The company said that it has produced all the models needed and is now working on 28nm silicon to prove the implementation.

"We use our own bit cell so we are not restricted to the foundry's Vmin which is a huge advantage," said Mark de Souza, chief executive at Silicon Basis. "Dropping the voltage makes a huge difference."

All of this comes from a new way of looking at the design of the cell which is currently being patented. Souza said that they communicated with experts in memory design and that found that nobody thought about designing the SRAM the way they have. He added, "It's all using standard rules and standard CMOS. It's an architectural difference that means we don't need to use sense amps and because we are using logic rules, we can go down to the logic voltage floor and possibly below that."

The architecture brings advantages with the compiler that are not to be underestimated, said Rob Beat, the designer of the new cell and Silicon Basis CTO. "Our single port compiler also outputs a one port register file. Because of the way the bit cell is designed we can use the same bit cell for dual port so the dual port compiler will do the dual port register file and asynchronous dual port memory," he explained.

The technology has been characterized on the TSMC 40nm node and outperforms the high speed bit cell, said de Souza. "This took us a little bit by surprise as we didn't design for speed," he said. "We did a lot of work at 40nm but what we are seeing from customers is that 28nm HPM is going to be a major node and we think there will be more new designs starting on 28nm than on 40nm."

The technology is also fully compatible with FinFet vertical structures being used in TSMCs 16nm process node.

- Nick Flaherty
  EE Times Europe





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