Synopsys unveils verification compiler sol'n
Synopsys Inc. has released a product intended for SoC verification technology and verification roadmaps. The Verification Compiler, according to the firm, is a complete portfolio of integrated, next-generation verification technologies that include advanced debug, static and formal verification, simulation, verification IP and coverage closure.
The technologies claim to offer five times performance improvement and a substantial increase in debug efficiency, enabling SoC design and verification teams to create a complete functional verification flow with a single product. The combination of next-generation technologies, integrated flows and a unique concurrent verification licensing model enables Verification Compiler to deliver three times productivity overall, directly addressing the growing SoC time-to-market challenge.
With mobile and the Internet of Things driving electronics growth, advanced SoC development faces exponential growth in verification complexity, new power efficiency requirements, increasing software content and tougher time-to-market pressures. Achieving verification closure for these complex SoCs requires a broad set of technologies including advanced debug, static and formal verification, low-power verification, verification IP and coverage closure.
To address this challenging verification landscape, Verification Compiler features a comprehensive set of next-generation technologies, including formal verification, SoC connectivity checking, SoC-scale clock domain crossing (CDC) checking, X-propagation simulation, native low power simulation, and advanced verification planning and management. Verification Compiler also includes the entire portfolio of Synopsys' next-generation verification IP, including the corresponding test suites, all integrated for advanced debug and high-performance simulation. By integrating these technologies in a single product, Verification Compiler enables SoC design and verification teams to better solve the growing technical and schedule challenges of SoC verification.
Verification Compiler addresses the sheer capacity challenges of verifying complex SoCs with a next-generation static and formal verification technology that is 3X to 5X higher in performance and capacity compared to other solutions available today, noted the firm. This technology includes formal property checking, low power static checking, CDC checks, SoC connectivity checks, advanced lint and sequential equivalence checking. Verification Compiler static and formal capabilities are fully compatible with the Synopsys Design Compiler and Synopsys IC Compiler use model and flows.
Verification Compiler's debug capabilities are built using technology from Synopsys' Verdi3, the industry's de-facto debug platform. Verification Compiler uses all of Verdi3's latest debug technology including numerous innovative debug capabilities that offer substantially increased debug efficiency. These new capabilities include Interactive Testbench (UVM-aware) Debug, Transaction Debug, HW/SW Debug, Power-Aware Debug, and Protocol-Aware Debug, all built on a unified, consistent and easy-to-use environment. Verification Compiler further adds substantial debug efficiency through the tight integration of these advanced debug capabilities with simulation, VIP, formal verification and coverage.
The Synopsys Verdi3 debug platform continues to be available as a standalone product. Verdi3 is an open platform enabling integration with other verification flows through the Fast Signal Data Base (FSDB) database as well as through Verdi Interoperability Apps (VIA). Accordingly, Verdi3 will continue to fully support major simulation, emulation, and formal verification products in the market.
Today's SoC verification flows require simultaneous use of various verification technologies by multiple teams across geographies. Furthermore, different points of the flow require different concentrations of technologies. These types of access bottlenecks greatly impact verification efficiency, cost and time-to-market. To address these bottlenecks, each Verification Compiler license includes three independent, concurrent keys: one key for all static and formal technologies; one key for simulation-related technologies (including all VIP); and one key for all debug technologies. These three keys can be used concurrently by a single user to enhance individual productivity, or they can be used independently by different individuals in the same company. This flexibility enables design teams to simultaneously perform multiple verification functions, achieving dramatic verification productivity improvements.
Verification Compiler is available now under limited customer availability, with general availability planned for December 2014.
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