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DSA technique pushes chip fabrication below 20nm

Posted: 04 Mar 2014  Print Version  Bookmark and Share

Keywords:DSA  lithography  20nm 

Speculations about the Moore's Law reaching its limits have prompted an MIT research on enabling semiconductor manufacturers to further shrink geometries below 20nm and produce advanced components cost effectively.

A team of MIT researchers claim that the directed self-assembly (DSA) technique they have developed work out the limitations concerning the two main lithography processes employed in the semiconductor manufacturing. At 193nm, photolithography is reaching its limit with feature sizes around 25nm. Whereas the throughput that can produce smaller features in electron-beam lithography is inadequate for sub-20nm resolution pattering over large areas.

Described as a hybrid process, the DSA technique is based on a simplified template, in which complex patterns of line, bends, and junctions with feature sizes below 20nm can be made using block copolymer self-assembly, according to the MIT study. It also explained how to design the template to achieve a desired pattern. Electron-beam lithography was used to produce the template serially, while the block copolymer filled in the rest of the pattern in a parallel process. DSA can be five or more times faster than writing the entire pattern by electron beam lithography, according to the MIT study.

"DSA is of great interest to manufacturers as scaling using traditional patterning techniques has become increasingly more challenging and costly," said Bob Havermann, Director of Nanomanufacturing Sciences at Semiconductor Research Corp., which sponsored the MIT report.

The alternatives to DSA would be continuing to reduce pattern sizes in conventional photolithography using double, quadruple, etc... patterning; to use extreme UV lithography which has much smaller wavelength and therefore better resolution; or to do direct write using electron beam lithography, said Caroline Ross, MIT professor of Materials Science and Engineering, Cambridge, Mass.

"Nanoimprint lithography may also be a viable process. Each of these has its own limitations and advantages, but overall DSA is a very attractive option because it provides scalability at high throughput and a lower cost than other processes," Ross said.

Leveraging block copolymer self-assembly to produce dense, high resolution patterns was proposed and demonstrated several years ago, but there was no systematic way to design templates to achieve a complex block copolymer pattern. The MIT study developed a simple way to design a template to achieve a specific block copolymer pattern over a large area. Although the work used electron-beam lithography to define the template, other methods such as photolithography with trimming could be used to produce the templates.

Photolithography was expected to fail when the feature sizes reached the wavelength of the UV light, 193nm. However, engineers discovered that patterning could be done using constructive and destructive superposition properties of light, according to Robert Colwell, Intel Corp.'s chief IA-32 Pentium chip architect in the 1990s, as well as an IEEE Fellow and a member of the National Academy of Engineering. As a result, the process required double exposure of the silicon, but the wavelength ceased to be the first-order determinant of the final feature size, he said.

"The industry has been riding that double-exposure idea for many years now, and now we're again approaching a fundamental limit," Colwell wrote in an email to EE Times, questioning whether the chip could be exposed a quadruple number of times. "In principle, yes, and maybe that's what industry will try next. But it's much more expensive (the cost of the mask sets alone will probably exceed $10 million), and may well result in lower yield, which at today's volumes is not a prospect anyone wants to entertain."

For decades, Moore's Law enabled semiconductor designers to double the number of transistors on a chip every two years, yielding higher-performance, more advanced parts with each generation. However, thermal power has become a major issue since Dennard scaling, the physics that once made the power density per unit area remain constant across process generations, has been dead for eight years, according to Colwell. In addition, power constraints are limiting clock rates and the interconnects between the transistors haven't improved, he added.

Still, Ross believes the latest MIT research will help Moore's Law continue.

"To increase the density of transistors in a given area, the pitch of the features in a transistor should be scaled down, but the increasing time and cost of manufacturing such fine and dense features becomes more problematic. Our research suggests a solution to this problem," she said.

- Ismini Scouras
  EE Times





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