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Intro to C-slow retiming, system hyper pipelining

Posted: 03 Mar 2014  Print Version  Bookmark and Share

Keywords:pipelining  C-slow retiming  CPU  RTL  verification 

I guess everybody knows what pipelining is, and that CPUs are pipelined to optimise their throughput. And we can all agree that inserting registers at the right places in the data path can improve throughput. It's certainly not a unique idea, and this technique is already used in various designs. Having said this, I think this method has a lot more potential—especially in the multi-core era—than many people realise. Let's talk about it.

The idea is all about reusing logic in a time-sliced fashion, scheduling, and synchronisation. The contrary asynchronous approach might appear sexy, but using asynchronous techniques will result in a total mess (to be a little bit provocative).

My history with C-slow retiming
As a student, I worked on a chip for a keyboard manufacturer with many different kinds of interfaces: PS2, I2C, RS232, smart card IF, matrix scan, bar code, and magnetic card decoder. The magnetic card decoder consumed a relatively huge chunk of the chip and had four identical designs—one for each track. This led me to the idea of multiplying the track decoder by inserting registers. I ended up writing my diploma thesis on this technique.

As an field application engineer for LSI Logic's MIPS processors, I enjoyed a few months working with the MIPS team in Milpitas, Calif. I realised that the multiplication of processors by inserting registers cannot be performed realistically by a design team using hand-crafting techniques. An automated approach is mandatory. I created an EDA tool that performs timing estimation on RTL and can automatically modify the RTL for things like register insertion.

In 2010, I decided to revive my student project and to further develop my EDA tool. I have spent a substantial amount of time on this subject. The more I dig into it, the more excited I become, especially with regard to multi-core system architectures.

The basics of C-slow retiming
Don't worry if you don't fully grasp the concept of CSR straight away. I once explained it to two engineers in front of a white board. One of the engineers got it immediately, but it took both of us an inordinate amount of time to explain it to the other engineer. Eventually, we gave up. It's like the classic picture shown in figure 1. Either you can see both the old woman and the young woman, or you don't. Once you do see both, you realise how simple it is.

Figure 1: Do you see both the old and the young woman in this image?

A theoretical example
Let's start by considering a simple circuit involving a two-input AND gate driving a second two-input AND gate. The output feeds the input of a register, as illustrated in figure 2.

Figure 2: Solving an equation in one cycle.


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