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Micron exec hints at novel memory chips, processors

Posted: 05 Feb 2014  Print Version  Bookmark and Share

Keywords:Micron Technology  memory chip  processor  Hybrid Memory Cube 

In a keynote at DesignCon, the chief technologist at Micron Technology said new types of memory interfaces and chips, and processors are coming that promise more performance and new capabilities for engineers who adopt them. Thomas Pawlowski outlined the general trend toward abstracted memory interfaces and new kinds of memory chips. He also gave a more detailed description of a promising processor architecture that Micron has in development.

The Hybrid Memory Cube "shows the shape of things to come" in abstracted memory interfaces. HMC is a dense stack of memory die in a package that breaks through memory-bandwidth limits with an interface that delivers 160Gb/s.

The HMC interface "exposes nothing, just a SerDes interface with a simple command set. All the details are not your problem." Such highly optimized interfaces built into DRAMs are the wave of the future. They will replace lowest-common-denominator standards hammered out between processor and memory vendors in committees that "left performance on the table for decades."

In an interview after the keynote, Pawlowski said the Jedec standards group has "nothing in the pipeline" after its DDR4 high-end DRAM interface. However it is developing a family of low-power DDR interfaces, as well as Wide I/O, an interface for attaching a memory chip directly to a processor.

Pawlowski gave a tip of the hat to memory architectures beyond the DRAM, but he said in the interview that it's still unclear which will win or when. The alternatives "certainly have been whittled down to fewer than we were exploring before." Micron has said it is working on spin-transfer torque RAM and phase-change memory. Phase-change memory "is in low-volume production" but is not suitable as a DRAM or NAND flash replacement. Even though "it has its place, it's its own thing."

Micron's process technology experts have expressed "wild disagreement" about when a DRAM replacement will be needed. "The earliest points to 2015, and the latest points to far enough out you could call it never."

Pawlowski was more specific about the Automata Processor (AP) that Micron announced last fall. He described it as a kind of symbol processor or state machine or, more accurately, a nondeterministic finite AP. It has the potential to solve highly complex problems in network security, bioinformatics and other fields that can't be cracked by conventional CPUs, GPUs or FPGAs, he said. This suggests it could have a vast addressable market. Micron is debugging a revision of the part produced in its DRAM fabs with hopes of sampling it as early as April.

Automata Processor

In theory, a single AP card will offer quick solutions to problems that baffle a large computer cluster.

A suite of four AP development tools will be released before June. One tool enables writing regular expressions for security apps; another uses Python as a scripting language along with visual tools for developers in bioinformatics.

Micron also designed a hardware developer's kit based on a PCIe board that will hold 48 of the processors. It also is exploring use of the AP on various kinds of memory cards such as DIMMs.

- Rick Merritt
  EE Times





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