Apple taps Samsung 28nm HKMG process for A7
Sinjin Dixon-Warren, team leader at Chipworks' Process Analysis Lab, breaks down the front end of line (FEOL) transistor structure used in Apple's A7.
The Apple A7 processor used inside the iPhone 5s represents an extraordinary piece of engineering. The A7 is fabricated with Samsung's 28nm low-power, gate-first, high-k metal gate (HKMG) process technology. The process features nine layers of copper metallisation with low-k dielectrics, plus an additional top aluminium metal layer. This piece will focus on the front end of line (FEOL) transistor structure used in the A7, with comparison to advanced technologies used by both Apple and other vendors. The A7 gate-first transistor structure is based on the Common Platform Technology, which is an alliance of IBM, Samsung, and GlobalFoundries.
Chipworks has analysed several generations of the Samsung process used to fabricate the A-series processors used in the iPhone and other Apple products. The A4 processor, released in September 2010, used a Samsung 45nm polysilicon transistor process technology with 180nm contacted gate pitch. The NMOS and PMOS transistor structures were essentially identical, with the main observable differences being in the materials used for the polysilicon gate and source/drain silicides.
Figure 1: Apple A4 45nm MOS transistors, image taken on transmission electron microscope.
Apple moved to a 10 metal, 32nm HKMG process when it launched the A5 processor in March 2011. The gate-first transistors featured a 130nm contacted gate pitch, with a SiGe channel for the PMOS transistors, and separate work function metals for the NMOS and PMOS transistors. The SiGe channel improves the PMOS hole mobility and serves as part of the transistor work function engineering. The A6 processor, launched in September 2012, was also built with the Samsung 32nm HKMG process.
The A7 is Apple's first 28nm device. The process technology is broadly similar to that used at 32nm, with an ~10 per cent shrink of the contacted gate pitch to 120nm. The PMOS and NMOS transistors are easily distinguished due to marked differences in the transistor structure.
The NMOS transistors feature an NMOS work function metal gate (MG) deposited onto the high-k (HK) gate dielectric, which is composed of hafnium oxide deposited over a thin layer of silicon dioxide. The process is described as gate-first since the silicided polysilicon gate is deposited after the HKMG gate stack has been formed.
Figure 2: A transmission electron microscope image of A7 28nm NMOS transistors.
The main distinguishing features of the PMOS transistors are the presence of a SiGe channel beneath the PMOS gates and a separate PMOS work function metal deposited over the HK dielectric stack.
The NMOS MG layer is present over the PMOS MG layer, indicating that the PMOS transistors were formed first in the process flow. This NMOS MG layer would have no effect on the electrical characteristics of the PMOS transistor, although it may serve as a barrier to protect the PMOS MG layer during the polysilicon deposition process step. There are minor differences in the shape of the sidewall spacer structure (SWS) for the PMOS as compared to the NMOS transistors, while both transistor types are sealed with the same contact etch stop layer (CESL).
Figure 3: Apple A7 28nm PMOS transistors.
The requirement for two different metal gates, with different work functions, is one of the major challenges for HKMG process technology. It is quite easily achieved in polysilicon gate technology through doping of the gate polysilicon as N-type for the NMOS and P-type for the PMOS transistors. A review of work function engineering has recently been published. Variations on the gate-first PMOS SiGe channel technology used for the A7 have been used by GlobalFoundries in the AMD 32nm devices, and by IBM in the Power 7+ processors.
By contrast, Intel and TSMC have avoided the use of SiGe in the PMOS channel region; they achieve the work function difference purely through engineering of the metal gates. Furthermore, Intel and TSMC used a gate replacement (gate-last) process, where the transistor engineering is completed using conventional polysilicon gates. The polysilicon is then removed and replaced with the NMOS and PMOS HKMG gate stack.
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