Synopsys, UMC team up to develop 14nm FinFET process
Synopsys Inc. and United Microelectronics Corp. (UMC) have joined forces to deliver a successful tape-out of UMC's first process qualification vehicle in its 14nm FinFET process using Synopsys' DesignWare Logic Library IP portfolio and StarRC parasitic extraction solution.
Due to its performance, power, intra-die variability and lower retention voltage over the planar CMOS process, the FinFET process is gaining significant interest from designers. This process qualification vehicle will provide early silicon data, enabling UMC to tune its 14nm FinFET process and Synopsys to refine its DesignWare IP portfolio for optimal power, performance and area. It also provides data to enable better correlation of the FinFET simulation models to the silicon results. This is the first milestone of an ongoing collaboration to validate UMC's 14nm FinFET processes using DesignWare IP solutions.
Synopsys' FinFET-ready DesignWare Logic Library IP portfolio consists of high-speed, high-density and low-power standard cell libraries that include multiple voltage threshold implementations and support multi-channel gate lengths to minimise leakage power. In addition, the available Power Optimisation Kits (POKs) and Engineering Change Order (ECO) Kits deliver outstanding performance with low power and small area, meeting the speed and density requirements of advanced SoCs.
The StarRC parasitic extraction tool offers advanced extraction capabilities at 14nm, based on precise 3D modelling of the parasitics found in FinFET devices. Due to its unique ability to describe the exact silicon profile of FinFET transistors, StarRC's embedded field solver generates highly accurate device model parasitics which enable 14nm IP developers to optimise their designs for maximum performance and lowest power. Synopsys' Galaxy Implementation Platform also provides designers with a full suite of implementation tools that are FinFET-ready.
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