3D stacking is the future of chip design, says Xilinx
"For many years, designers kept digital-logic, -memory and analogue functions on separate chips—each taking advantage of different process technologies," said Madden. "On the other side are system-on-chip [SoC] solutions, which integrate all three functions on the same die. However now there is a third alternative that takes advantage of both worlds—namely 3D stacking."
Madden believes that Fred Weber, former chief technology officer at Advanced Micro Devices Inc., may have said it best when he said: "Integrate or be integrated."
For years, this knee-jerk reaction drove processor designers to integrate more-and-more peripheral functions out of fear that other companies would beat them to the punch and become so successful that they eventually acquire them. Eventually, the success of the monolithic integration approach prompted designers to begin integrating memory and analogue functions onto processors, too, resulting it SoCs.
Madden proposes using silicon interposers to integrate separate dies for processing, memory and analogue into 3D stacks, thus combining the best of both worlds—increased density that to programmers looks exactly like an SoC, but by retaining the ability to using different processes technologies each optimised for their assigned task.
Xilinx's first implementation was its homogeneous Virtex-7 H580T, which combined four Xilinx FPGAs into a single package, integrated by a silicon interposer built by Taiwan Semiconductor Manufacturing Co. (TSMC). However, its latest 3D chip stack, the Virtex-7 H580T, is heterogeneous—combining two FPGAs with the a 2.8Gbit/s transceiver and , there by implementing a SerDes that is the only single-chip solution for 400Gbit/s line cards.
For the future, Xilinx plans to continue integrating heterogeneous die with silicon interposers, in order to combine the best of both worlds, with its next slated offering the Virtex-7 H870T which uses a silicon interposer to integrate three FPGA die with two 28-Gbit per second transceivers and the necessary analogue functions in the same package.
Others sessions in the symposium's 3D integration track included Taiwan's Industrial Technology Research Institute scientist, Pei-Wen Luo, presenting benchmarking methods for 3D power delivery networks. Dresden University of Technology researcher Robert Fischbach presented 3D floor-planning techniques using reusable rectilinear IP blocks. And Universitat Politecnica de Catalunya researcher Jordi Cortadella presented physical-aware system-level design methods for creating 3D tiled hierarchical chip multi-processors.
- R. Colin Johnson
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