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Self-assembled monolayers create p-n junctions in graphene

Posted: 12 Dec 2012  Print Version  Bookmark and Share

Keywords:p-n junction  grapheme film  chemical vapor deposition  self-assembled monolayer 

A team of researchers at the Georgia Institute of Technology has created graphene p-n junctions—which are essential to fabricating devices—without damaging the material's lattice structure or significantly reducing electron/hole mobility. The electronic properties of graphene films are directly affected by the characteristics of the substrates on which they are grown or to which they are transferred. Researchers are taking advantage of this to create graphene p-n junctions by transferring films of the promising electronic material to substrates that have been patterned by compounds that are either strong electron donors or electron acceptors, the team noted.

A low temperature, controllable and stable method has been developed to dope graphene films using self-assembled monolayers (SAM) that modify the interface of graphene and its support substrate. The graphene was grown on a copper film using chemical vapor deposition (CVD), a process that allows synthesis of large-scale films and their transfer to desired substrates for device applications. The graphene films were transferred to silicon dioxide substrates that were functionalized with the SAM.

The Georgia Tech research team working on the project includes faculty members, postdoctoral fellows and graduate students from three different schools.

Creating n-type and p-type doping in grapheme—which has no natural bandgap—has led to development of several approaches. Scientists have substituted nitrogen atoms for some of the carbon atoms in the graphene lattice, compounds have been applied to the surface of the graphene, and the edges of graphene nanoribbons have been modified. However, most of these techniques have disadvantages, including disruption of the lattice, which reduces electron mobility, and long-term stability issues.

Using conventional lithography techniques, the researchers created patterns from different silane materials on a dielectric substrate, usually silicon oxide. The materials were chosen because they are either strong electron donors or electron acceptors. When a thin film of graphene is placed over the patterns, the underlying materials create charged sections in the graphene that correspond to the patterning.

The monolayers are bonded to the dielectric substrate and are thermally stable up to 200°C with the graphene film over them. The Georgia Tech team has used 3-Aminopropyltriethoxysilane (APTES) and perfluorooctyltriethoxysilane (PFES) for patterning. In principle, however, there are many other commercially-available materials that could also create the patterns.

The researchers used their technique to fabricate graphene p-n junctions, which was verified by the creation of field-effect transistors (FET). Characteristic I-V curves indicated the presence of two separate Dirac points, which indicated an energy separation of neutrality points between the p and n regions in the graphene.

The group uses chemical vapor deposition to create thin films of graphene on copper foil. A thick film of PMMA was spin-coated atop the graphene, and the underlying copper was then removed. The polymer serves as a carrier for the graphene until it can be placed onto the monolayer-coated substrate, after which it is removed.

Beyond developing the doping techniques, the team is also exploring new precursor materials that could allow CVD production of graphene at temperatures low enough to permit fabrication directly on other devices. That could eliminate the need for transferring the graphene from one substrate to another.

A low-cost, low-temperature means of producing graphene could also allow the films to find broader applications in displays, solar cells and OLEDs, where large sheets of graphene would be needed.





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