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Samsung goes quad-core

Posted: 23 Feb 2012  Print Version  Bookmark and Share

Keywords:Exynos  HKMG process 

Samsung Electronics Co. Ltd gave an early peek at its first quad-core mobile application processor at the International Solid-State Circuits Conference (ISSCC).�The unannounced chip is Samsung's first to use its 32nm high-k metal gate process and sports advances in performance and battery life over its existing 45nm Exynos chips.

The new chip comes in versions using two or four ARM Cortex A9 cores running at rates from 200MHz to 1.5GHz along with a 64bit ARM Neon media processing block. The cores share a 1MB L2 cache with a snoop control unit. The chip does not include an integrated baseband.

Samsung is using the latest version of its own graphics unit for the chip. It includes four pixel processors and one geometry engine with a dedicated 128KB L2 cache. The graphics support the OpenGL ES 2.0 API and can generate up to 57Mpolygons/s.

The chip supports two LPDDR2 or DDR3 interfaces running up to 400MHz for a total memory bandwidth of up to 6.4GB/s.

Thanks both to the 32nm process and a handful of power and thermal management techniques, the chip can deliver up to 26 percent more performance overall than Samsung's current Exynos chip made in a 45 nm polysilicon process. It also can deliver improvements in battery life ranging from 34 to 50 percent, depending on the application.

Samsung said the new chip delivers up to 26.3 percent improvements in video frame rates. In a demo, Samsung showed the chip using 48 percent less power on 3D calculations and 45 percent less power in CPU jobs than the 45nm chip.

The Samsung 32nm HKMG process keep transistor and gate leakage nearly to the levels of the company's 45 nm polysilicon process, much lower than expected for 32 nm polysilicon technology. Samsung tuned the process to a sweet spot somewhere between its potential for delivering 40 percent more performance or a tenth the leakage, said Se-Hyung Yang, a principal engineer for SoC development at Samsung Electronics who presented the paper.

The chip has four independent power domains and several power sub-domains. Each ARM core and up to a half of the cache memory can be turned off or on independently. A set of media accelerator blocks are similarly power gated independently.

The chip dynamically uses either forward or reverse body-biasing on n-wells to improve performance or reduce leakage as needed. It also uses thermal monitors and a thermal management unit to trigger power management actions including shutting down blocks as needed to protect devices from over-heating and keep a handset below a fixed surface temperature set by handset makers.

"Recently power consumption for mobile devices have increased a lot and mobile devices have limited cooling capability," said Yang, underlining a growing problem in smartphone design.

Samsung optimized its 45nm processor for performance first and later found it could not get its full performance without exceeding power consumption limits. The 32 nm chip was optimized first for power consumption, said Yang.

Samsung will formally announce the product soon, said Yang, presumably at next week's Mobile World Congress. Nvidia grabbed the lead in rolling out a quad-core mobile chip last year.

- Rick Merritt
  EE Times





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