Issues of EUV lithography
EUV was originally planned for production use as far back as 2005. It had been expected to be ready for 22nm chip manufacture, which Intel is initiating this year. However, Intel Corp. now plans to extend optical lithography through the 14nm node and switch to EUV as its mainstream production approach at the 10nm node, starting in the second half of 2015. Samsung plans to insert EUV into volume manufacturing as soon as 2013.
Chip makers need EUV to be ready well in advance of when they plan to use it in volume manufacturing so they can establish chip design rules and tweak their manufacturing processes. There are still challenges for EUV, including the development of better photomask inspection and repair tools and more-sensitive photoresists.
By far, the biggest hurdle to rolling out EUV in volume production is wafer throughput on EUV tools, a metric that remains far lower than what is needed to make EUV-based manufacturing viable. The gating factor on throughput has been the lack of a EUV light source that can deliver the necessary power and reliability.
ASML, the leading vendor of photolithography gear, has sold six preproduction EUV tools to chip companies. Three of the systems are now being used to expose wafers. The others are in various stages of installation and shipment to customers, according to Bill Arnold, ASML's chief scientist. The vendor acknowledges that the tools have throughput of fewer than 10 wafers per hour. Some observers say it's between one and five wafers per hour.
Several manufacturers have tried, but thus far failed, to develop an EUV light source that is sufficiently powerful and reliable to support EUV lithography with adequate throughput. ASML has whittled the list of possible saviors to three companies: Ushio, GigaPhoton and longtime ASML supplier Cymer.
ASML said last month that two power source suppliers had demonstrated technologies for power levels that should help improve the throughput of EUV scanners to about 15 wafers per hour. That would put the equipment company on a road map to improve throughput to "commercially viable levels" by summer 2012, it said.
Some observers remain confident that ASML will nudge its suppliers to develop a suitable source and that EUV will move into volume production by 2015. Skeptics—including some of EUV's biggest proponents—wonder if more brainpower and elbow grease are needed or whether power source developers are fighting a no-win battle with the laws of physics.
Europe's Interuniversity Microelectronics Center, a flagship center for EUV lithography research, announced in July that it was exposing EUV wafers with an ASML preproduction tool. But Imec, as well, is making contingency arrangements; CEO Luc Van den Hove said recently that it would take delivery of ASML's latest 193nm immersion litho tool to handle optical lithography development work as a "backup plan" in case EUV missed the 14nm node.
But at 14nm and beyond, double patterning with optical immersion lithography no longer has sufficient resolution to write mask features; triple, quadruple or even quintuple patterning will be required, insiders said.
Using as many as five photomasks for critical layers where previously only one was needed would add considerable cost to any design start. But it's unclear to what degree that premium would be an issue, since EUV itself is not exactly a cheap date. Some equipment market watchers say the cost of production EUV tools could come in at more than $100 million.
- Dyaln McGrath
Adapted from EE Times Confidential
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