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Graphene enables 2GHz doubler IC

Posted: 21 Sep 2011  Print Version  Bookmark and Share

Keywords:graphene IC  CMOS  manufacturing process 

Researchers from IBM Corp. have developed a CMOS-compatible manufacturing process that integrates multiple graphene FETs and RF passives on a frequency doubler circuit.

Graphene, a honeycomb lattice of carbon atoms in a single-sheet, holds an electric field effect and ballistic electronic transport. The electron mobility of graphene is higher than that of silicon by at least a factor of 40. While properties including high current density, mobility and saturation velocity make the material ideal for high performance circuits, working with carbon is difficult. It is known to be problematic when introduced into a wafer fab, the researchers said.

IBM's paper intends to establish a manufacturable technology based on CMOS-compatible fabrication on 200mm diameter wafers. Because all the carbon chemical bonds are used within a perfect graphene sheet, it has an inherently inert surface making the fabrication of a dielectric layer above it—to insulate the gate—difficult. IBM's approach has been to invert the usual manufacturing process and define gate structures first on silicon wafers and then transfer graphene layers fabricated using chemical vapor deposition to the silicon. After defining the areas of graphene, IBM was able to attach source and drain contacts to the graphene to complete FET structures.

The frequency doubler showed conversion gain of about -25db at an output frequency of 2GHz.

post-CMP wafer

Cross-sectional scanning electron microscope micrograph of the post-CMP wafer showing the inverted-T gate structure described in the paper.

CMOS-compatible manufacturing process

The four images show: (a) an 8-inch (convert to mm except for displays) graphene FET wafer; (b) single die; (c) SEM image of a typical fully processed device and (d) an enlarged view of the device showing the embedded gate structure with two-finger design.

Except for the CVD graphene transfer, all processing was done in a conventional 200mm wafer fab.

- Peter Clarke
  EE Times





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