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Samsung chief cites challenges facing IC design

Posted: 24 Feb 2011  Print Version  Bookmark and Share

Keywords:FinFET  3D NAND  TSV  read-assist  write-assist 

Oh-Hyun Kwon, president of Samsung Electronics Co. Ltd's semiconductor business, cited and explained the four key challenges confronting next-generation IC design and scaling. Delivering the keynote at the 2011 International Solid-State Circuits Conference (ISSCC), Kwon also dwelled on phase-change memory and green manufacturing.

The four challenges that IC design and scaling must contend with are:

1. Power consumption
Needless to say, ICs are power-hungry. When the industry moved from 180nm to 90nm chip designs, IC makers were able to cut dynamic power by about 30 percent per node, Kwon said. "However, beyond 90nm, we experienced the well-known short-channel effects, which make it hard to lower the operating voltage," he said.

The industry also continues to wrestle with gate-leakage. To solve some of those issues, leading-edge chipmakers have moved or will move to high-k and metal gates for the gate stack. This in turn will reduce dynamic power consumption by 20 percent, according to Kwon.

But that is still not enough. The overall goal is to reduce power consumption by a compound annual rate of 20 percent over the next decade.

2. Next-generation transistor and memory
Beyond the 20nm logic node, today's planar transistors could run out of gas. At 14nm, the industry will require a new transistor structure. Next-generation transistor candidates include multigate, FinFET, fully-depleted silicon-on-insulator (SOI), 3D devices, among others.

According to Kwon, FinFET is a "strong candidate" beyond the 20nm node. For example, combined with a high-k/metal-gate scheme, a FinFET with high-k can reduce power by up to 10 percent, while performance is expected to improve by 20 percent, he said.

He said that it is still unclear how far today's memory technology—such as DRAM, NAND and NOR—can scale. Samsung itself is developing a range of next-generation replacement technologies, such as 3D NAND, MRAM, PRAM and ReRAM.

But there has been an overall reluctance by the systems houses to adopt the various next-generation memory technologies. He urged OEMs to collaborate more with the memory houses in order to get wider adoption for the next-generation memory types.

3. Let's go 3D
Bringing 3D devices based on through-silicon via (TSV) is taking longer than expected. But at ISSCC, Samsung announced the development of a 1Gb DRAM with a 512-pin wide I/O interface intended for mobile applications such as smartphones and tablet computers. The chip is implemented in a manufacturing process technology somewhere between 50- and 59nm.

It will be reportedly housed in a 3D package, based on TSV technology. Shipments are targeted for 2013.

"The wide I/O memory interface enabled by TSV technology offers considerable power reduction (up to 75 percent) by reducing the load capacitance of interconnect and I/O circuits," Kwon said.

4. New breakthroughs needed in circuit design
"Commonly-used low-power circuit-design techniques include clock gating, clock-tree gating, power gating, multithreshold/multichannel libraries, and voltage islands," he said. "However, circuit structures sensitive to process variation tend to be unstable at lower voltages, limiting the extent of voltage down-scaling."

Embedded SRAM are particularly sensitive to process variation. "To overcome this problem, SRAM designers have employed various techniques: one of them is the read-assist and write-assist circuit technique, which improves SRAM cell stability," Kwon stated.

Replacing today's "6-transistor (6T) memory cells with 8-transistor (8T) cells is (also) an attractive option," he added.

- Mark LaPedus
  EE Times





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