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Micron debuts 'first' DDR3 load-reduced DIMM

Posted: 05 Aug 2009  Print Version  Bookmark and Share

Keywords:DDR3  DIMM  LRDIMM  DRAM 

Micron Technology Inc. has rolled out what it claims to be the industry's first DDR3 load-reduced DIMM (LRDIMM).

The new LRDIMMs will be manufactured using Micron's 1.35V, 2Gbit 50nm DDR3 memory chips. By reducing load on the server memory bus, Micron's LRDIMMs provide the option to support higher data frequencies and increased memory capacity.

Micron's LRDIMMs currently use Inphi's isolation memory buffer chip in place of a register to reduce the bus load when transferring data between the memory and processor. Micron's new LRDIMMs reduce this load by 50 percent for a dual-rank module and 75 percent for a quad-rank module, compared to today's standard DDR3 server modules—registered DIMMs (RDIMMs).

Today, using RDIMMs, a typical server system can accommodate up to three quad-rank 16Gbyte RDIMMS per processor. However, that same system can support up to nine quad-rank 16Gbyte LRDIMMS per processor, pushing the memory capacity from 48- to 144Gbyte.

Measuring performance levels, Micron's 16Gbyte LRDIMM offers an increase of 57 percent in system memory bandwidth, when compared to an RDIMM. And as server power consumption continues to be a top concern for customers, Micron's LRDIMMs will also operate at the industry's lowest 1.35V.

"With the rise in virtualization, our new 16Gbyte modules allow customers to easily expand their memory capacity. While traditional RDIMMs limit the amount of memory that can be accommodated due to their loading profile, LRDIMMs eliminate that problem by reducing the module load," said Robert Feurle, VP of DRAM marketing at Micron, in a statement.

Micron is currently sampling an 8Gbyte LRDIMM with select enablers. Mass production of its 16Gbyte LRDIMMs is expected to begin in 2010.

- Mark LaPedus
EE Times





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